From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 16 Feb 2022 00:54:26 +0000 (+0000)
Subject: * disable DDR3 for now
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ad1e951155df66d277fa0b031959b6a01e77e4e;p=ls2.git

* disable DDR3 for now
* reduce bootrom size
* add external_core_top.v when building for VERSA_ECP5
---

diff --git a/src/ls2.py b/src/ls2.py
index 7949dda..43dd0d2 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -83,7 +83,7 @@ class DDR3SoC(SoC, Elaboratable):
         # SRAM (but actually a ROM, for firmware), at address 0x0
         if fw_addr is not None:
             sram_width = 32
-            self.bootmem = SRAMPeripheral(size=0x10000, data_width=sram_width,
+            self.bootmem = SRAMPeripheral(size=0x8000, data_width=sram_width,
                                       writable=True)
             with open(firmware, "rb") as f:
                 words = iter(lambda: f.read(sram_width // 8), b'')
@@ -96,9 +96,10 @@ class DDR3SoC(SoC, Elaboratable):
                                       has_uart=(uart_pins is not None))
         self._decoder.add(self.syscon.bus, addr=0xc0000000) # at 0xc000_0000
 
-        # SRAM (read-writeable BRAM)
-        self.ram = SRAMPeripheral(size=4096)
-        self._decoder.add(self.ram.bus, addr=0x8000000) # SRAM at 0x8000_0000
+        if False:
+            # SRAM (read-writeable BRAM)
+            self.ram = SRAMPeripheral(size=4096)
+            self._decoder.add(self.ram.bus, addr=0x8000000) # at 0x8000_0000
 
         # UART at 0xC000_2000, convert 32-bit bus down to 8-bit in an odd way
         if uart_pins is not None:
@@ -147,7 +148,8 @@ class DDR3SoC(SoC, Elaboratable):
         if hasattr(self, "bootmem"):
             m.submodules.bootmem = self.bootmem
         m.submodules.syscon = self.syscon
-        m.submodules.ram = self.ram
+        if hasattr(self, "ram"):
+            m.submodules.ram = self.ram
         if hasattr(self, "uart"):
             m.submodules.uart = self.uart
             comb += self.uart.cts_i.eq(1)
@@ -192,16 +194,24 @@ class DDR3SoC(SoC, Elaboratable):
             # wire up the CPU interrupts
             comb += self.cpu.irq.eq(self.intc.ip)
 
+        if platform is None:
+            return m
+
         # add uart16550 verilog source. assumes a directory
         # structure where ls2 has been checked out in a common
         # subdirectory as https://github.com/freecores/uart16550
-        if platform is not None:
-            opencores_16550 = "../../uart16550/rtl/verilog"
-            pth = os.path.split(__file__)[0]
-            pth = os.path.join(pth, opencores_16550)
-            fname = os.path.abspath(pth)
-            print (fname)
-            self.uart.add_verilog_source(fname, platform)
+        opencores_16550 = "../../uart16550/rtl/verilog"
+        pth = os.path.split(__file__)[0]
+        pth = os.path.join(pth, opencores_16550)
+        fname = os.path.abspath(pth)
+        print (fname)
+        self.uart.add_verilog_source(fname, platform)
+
+        # add the main core
+        pth = os.path.split(__file__)[0]
+        pth = os.path.join(pth, '../external_core_top.v')
+        with open(pth) as f:
+            platform.add_file('external_core_top.v', f)
 
         return m
 
@@ -241,15 +251,16 @@ if __name__ == "__main__":
         firmware = sys.argv[2]
         fw_addr = 0x0000_0000
 
+    ddr_pins = None
     if platform is not None:
         # get DDR and UART resource pins
-        ddr_pins = platform.request("ddr3", 0,
+        if False:
+            ddr_pins = platform.request("ddr3", 0,
                                     dir={"dq":"-", "dqs":"-"},
                                     xdr={"clk":4, "a":4, "ba":4, "clk_en":4,
                                          "odt":4, "ras":4, "cas":4, "we":4})
         uart_pins = platform.request("uart", 0)
     else:
-        ddr_pins = None
         uart_pins = Record([('tx', 1), ('rx', 1)], name="uart_0")
 
     # set up the SOC