From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 30 May 2019 20:07:29 +0000 (-0700)
Subject: Remove whitebox attribute from DRAMs for now
X-Git-Tag: working-ls180~1208^2~231
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ad33c3b5ac91fc4e6cb6e2ff4b606a693838c2b;p=yosys.git

Remove whitebox attribute from DRAMs for now
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 120370860..7337e0ea7 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc_box_id = 4, lib_whitebox *)
+(* abc_box_id = 4 /*, lib_whitebox*/ *)
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -301,7 +301,7 @@ module RAM64X1D (
 `endif
 endmodule
 
-(* abc_box_id = 5, lib_whitebox *)
+(* abc_box_id = 5 /*, lib_whitebox*/ *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D, WCLK, WE,