From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 15 May 2019 06:48:51 +0000 (+0100)
Subject: very weird: invert readable vector, cscore works
X-Git-Tag: div_pipeline~2045
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1adb9707ba4ff90f0e13220228f2ef5f31360b3d;p=soc.git

very weird: invert readable vector, cscore works
---

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index d9e0108d..2edf6587 100644
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -10,6 +10,7 @@ class ComputationUnitNoDelay(Elaboratable):
         self.rwid = rwid
         self.alu = alu
 
+        self.counter = Signal(3)
         self.go_rd_i = Signal(reset_less=True) # go read in
         self.go_wr_i = Signal(reset_less=True) # go write in
         self.issue_i = Signal(reset_less=True) # fn issue in
@@ -51,7 +52,13 @@ class ComputationUnitNoDelay(Elaboratable):
 
         # outputs
         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
-        m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # request release out
+
+        with m.If(self.go_rd_i):
+            m.d.sync += self.counter.eq(1)
+        with m.If(self.counter > 0):
+            m.d.sync += self.counter.eq(self.counter - 1)
+        with m.If(self.counter == 1):
+            m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # req release out
 
         # create a latch/register for src1/src2
         latchregister(m, self.src1_i, self.alu.a, src_l.q)
diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 9a729be3..8003c54f 100644
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -335,6 +335,8 @@ def scoreboard_sim(dut, alusim):
         for i in range(len(dut.int_insn_i)):
             yield dut.int_insn_i[i].eq(0)
         yield
+        yield
+        yield
         while True:
             issue_o = yield dut.issue_o
             if issue_o:
@@ -342,6 +344,10 @@ def scoreboard_sim(dut, alusim):
             yield
 
 
+    yield
+    yield from print_reg(dut, [3,4,5])
+    yield
+    yield from print_reg(dut, [3,4,5])
     yield
     yield from print_reg(dut, [3,4,5])
     yield
diff --git a/src/regfile/regfile.py b/src/regfile/regfile.py
index 1d732ba8..29fbda65 100644
--- a/src/regfile/regfile.py
+++ b/src/regfile/regfile.py
@@ -10,7 +10,7 @@ import operator
 
 
 class Register(Elaboratable):
-    def __init__(self, width, writethru=True):
+    def __init__(self, width, writethru=False):
         self.width = width
         self.writethru = writethru
         self._rdports = []
diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index 1e597cda..af7b0ea2 100644
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -126,6 +126,7 @@ class FnUnit(Elaboratable):
         for i in range(self.n_dests):
             m.d.comb += self.xx_pend_o[i].eq(0)  # initialise all array
             m.d.comb += self.writable_o[i].eq(0) # to zero
+            m.d.comb += self.readable_o[i].eq(0) # to zero
 
         # go_wr latch: reset on go_wr HI, set on issue
         m.d.comb += wr_l.s.eq(self.issue_i)
@@ -161,8 +162,10 @@ class FnUnit(Elaboratable):
 
         # readable output signal
         g_rd = Signal(self.reg_width, reset_less=True)
+        ro = Signal(reset_less=True)
         m.d.comb += g_rd.eq((~self.g_wr_pend_i) & self.rd_pend_o)
-        m.d.comb += self.readable_o.eq(g_rd.bool())
+        m.d.comb += ro.eq(g_rd.bool())
+        m.d.comb += self.readable_o.eq(ro)
 
         # writable output signal
         g_wr_v = Signal(self.reg_width, reset_less=True)
diff --git a/src/scoreboard/global_pending.py b/src/scoreboard/global_pending.py
index eb9da598..51a05d3a 100644
--- a/src/scoreboard/global_pending.py
+++ b/src/scoreboard/global_pending.py
@@ -25,10 +25,11 @@ class GlobalPending(Elaboratable):
           on a particular register (extremely unusual), they must set a Const
           zero bit in the vector.
     """
-    def __init__(self, dep, fu_vecs):
+    def __init__(self, dep, fu_vecs, sync=False):
         self.reg_dep = dep
         # inputs
         self.fu_vecs = fu_vecs
+        self.sync = sync
         for v in fu_vecs:
             assert len(v) == dep, "FU Vector must be same width as regfile"
 
@@ -43,7 +44,10 @@ class GlobalPending(Elaboratable):
             for v in self.fu_vecs:
                 vec_bit_l.append(v[i])             # fu bit for same register
             pend_l.append(Cat(*vec_bit_l).bool())  # OR all bits for same reg
-        m.d.comb += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
+        if self.sync:
+            m.d.sync += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
+        else:
+            m.d.comb += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
 
         return m