From: lkcl <lkcl@web>
Date: Sat, 16 Jul 2022 12:01:33 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1177
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ade08f2d1e641a463edc910c19df75b389cefef;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index ce0c4e789..bff6fe3c4 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -51,10 +51,9 @@ There are three types of REMAP:
 * **FFT/DCT**, with full triple-loop in-place support: limited to
   Power-2 RADIX
 * **Indexing**, for any general-purpose reordering, also includes
-  limited 2D reshaping. Currently
-  under development.
+  limited 2D reshaping.
 
-# Principle
+# Basic principle
 
 * normal vector element read/write of operands would be sequential
   (0 1 2 3 ....)
@@ -78,7 +77,7 @@ arbitrary remapping the `Indexed` REMAP may be used.
   otherwise usual `0..VL-1` hardware for-loop
 * `svremap` to set which registers a given reordering is to apply to
   (RA, RT etc)
-* `sv.instruction` where any Vectorised register marked by `svremap`
+* `sv.{instruction}` where any Vectorised register marked by `svremap`
   will have its ordering REMAPPED according to the schedule set
   by `svshape`.
 
@@ -87,17 +86,17 @@ matrix to create
 a 5x4 result:
 
     svshape 5, 4, 3, 0, 0
-    svremap 31, 1, 2, 3, 0, 0, 0, 0
+    svremap 15, 1, 2, 3, 0, 0, 0, 0
     sv.fmadds 0.v, 8.v, 16.v, 0.v
 
 * svshape sets up the four SVSHAPE SPRS for a Matrix Schedule
-* svremap activates all five registers RA RB RC RT RS (31)
+* svremap activates four out of five registers RA RB RC RT RS (15)
 * svremap requests:
   - RA to use SVSHAPE1
   - RB to use SVSHAPE2
   - RC to use SVSHAPE3
   - RT to use SVSHAPE0
-  - RS to use SVSHAPE0
+  - RS Remapping to not be activated
 * sv.fmadds has RT=0.v, RA=8.v, RB=16.v, RC=0.v
 * With REMAP being active each register's element index is
   *independently* transformed using the specified SHAPEs.