From: Clint Smullen Date: Mon, 10 Nov 2008 19:51:18 +0000 (-0800) Subject: O3CPU: Make the instcount debugging stuff per-cpu. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1adfe5c7f3368c4225ff685ddcd66b6280c7599f;p=gem5.git O3CPU: Make the instcount debugging stuff per-cpu. This is to prevent the assertion from firing if you have a large multicore. Also make sure that it's not compiled in when NDEBUG is defined --- diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 3520fafaa..f40616e54 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -258,9 +258,6 @@ class BaseDynInst : public FastAlloc, public RefCounted public: - /** Count of total number of dynamic instructions. */ - static int instcount; - #ifdef DEBUG void dumpSNList(); #endif diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index 66075c60a..4ee7d2f2c 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -168,18 +168,21 @@ BaseDynInst::initVars() // Initialize the fault to be NoFault. fault = NoFault; - ++instcount; +#ifndef NDEBUG + ++cpu->instcount; - if (instcount > 1500) { + if (cpu->instcount > 1500) { #ifdef DEBUG cpu->dumpInsts(); dumpSNList(); #endif - assert(instcount <= 1500); + assert(cpu->instcount <= 1500); } - DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n", - seqNum, instcount); + DPRINTF(DynInst, + "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n", + seqNum, cpu->name(), cpu->instcount); +#endif #ifdef DEBUG cpu->snList.insert(seqNum); @@ -199,10 +202,13 @@ BaseDynInst::~BaseDynInst() fault = NoFault; - --instcount; +#ifndef NDEBUG + --cpu->instcount; - DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n", - seqNum, instcount); + DPRINTF(DynInst, + "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n", + seqNum, cpu->name(), cpu->instcount); +#endif #ifdef DEBUG cpu->snList.erase(seqNum); #endif diff --git a/src/cpu/o3/base_dyn_inst.cc b/src/cpu/o3/base_dyn_inst.cc index 3cf89e1b6..510109d8a 100644 --- a/src/cpu/o3/base_dyn_inst.cc +++ b/src/cpu/o3/base_dyn_inst.cc @@ -34,7 +34,3 @@ // Explicit instantiation template class BaseDynInst; - -template <> -int -BaseDynInst::instcount = 0; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 26c155262..7320d5638 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -159,6 +159,9 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) itb(params->itb), dtb(params->dtb), tickEvent(this), +#ifndef NDEBUG + instcount(0), +#endif removeInstsThisCycle(false), fetch(this, params), decode(this, params), diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index c60c20d55..d24e8c383 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -576,6 +576,11 @@ class FullO3CPU : public BaseO3CPU void dumpInsts(); public: +#ifndef NDEBUG + /** Count of total number of dynamic instructions in flight. */ + int instcount; +#endif + /** List of all the instructions in flight. */ std::list instList; diff --git a/src/cpu/ozone/base_dyn_inst.cc b/src/cpu/ozone/base_dyn_inst.cc index 5a3a69dff..e0570fd16 100644 --- a/src/cpu/ozone/base_dyn_inst.cc +++ b/src/cpu/ozone/base_dyn_inst.cc @@ -33,7 +33,3 @@ // Explicit instantiation template class BaseDynInst; - -template <> -int -BaseDynInst::instcount = 0; diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index cc371ed93..6b5e7282d 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -287,6 +287,11 @@ class OzoneCPU : public BaseCPU // main simulation loop (one cycle) void tick(); +#ifndef NDEBUG + /** Count of total number of dynamic instructions in flight. */ + int instcount; +#endif + std::set snList; std::set lockAddrList; private: diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index 93848c03f..1402f4b72 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -94,6 +94,9 @@ OzoneCPU::OzoneCPU(Params *p) #else : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this, p->width), +#endif +#ifndef NDEBUG + instcount(0), #endif comm(5, 5) {