From: Kazu Hirata Date: Fri, 30 Apr 2004 16:27:30 +0000 (+0000) Subject: bb-reorder.c, [...]: Fix comment typos. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ae58c30e27a46925523033fe3f5aa20f7b6b4d0;p=gcc.git bb-reorder.c, [...]: Fix comment typos. * bb-reorder.c, c-opts.c, cfglayout.c, cgraph.c, cgraphunit.c, cppfiles.c, fold-const.c, ggc-zone.c, loop-doloop.c, optabs.c, reg-stack.c, varasm.c, config/alpha/ev4.md, config/alpha/ev5.md, config/alpha/ev6.md, config/arm/arm.c, config/c4x/c4x.c, config/c4x/c4x.md, config/cris/cris.c, config/cris/cris.h, config/fr30/fr30.h, config/frv/frv.c, config/frv/frv.h, config/frv/frv.md, config/h8300/h8300.c, config/i386/i386.c, config/i386/i386.md, config/i386/winnt.c, config/ia64/itanium2.md, config/ip2k/ip2k.c, config/mips/mips.c, config/mips/mips.h, config/mips/sr71k.md, config/pa/pa.c, config/s390/s390.c, config/sh/sh.c: Fix comment typos. From-SVN: r81345 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 286fa74c4e3..57085d84f4f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2004-04-30 Kazu Hirata + + * bb-reorder.c, c-opts.c, cfglayout.c, cgraph.c, cgraphunit.c, + cppfiles.c, fold-const.c, ggc-zone.c, loop-doloop.c, optabs.c, + reg-stack.c, varasm.c, config/alpha/ev4.md, + config/alpha/ev5.md, config/alpha/ev6.md, config/arm/arm.c, + config/c4x/c4x.c, config/c4x/c4x.md, config/cris/cris.c, + config/cris/cris.h, config/fr30/fr30.h, config/frv/frv.c, + config/frv/frv.h, config/frv/frv.md, config/h8300/h8300.c, + config/i386/i386.c, config/i386/i386.md, config/i386/winnt.c, + config/ia64/itanium2.md, config/ip2k/ip2k.c, + config/mips/mips.c, config/mips/mips.h, config/mips/sr71k.md, + config/pa/pa.c, config/s390/s390.c, config/sh/sh.c: Fix + comment typos. + 2004-04-30 Paul Brook * config.gcc: Default ep9312 to hard-float. diff --git a/gcc/bb-reorder.c b/gcc/bb-reorder.c index e60151836e1..5437b8b0349 100644 --- a/gcc/bb-reorder.c +++ b/gcc/bb-reorder.c @@ -901,7 +901,7 @@ connect_traces (int n_traces, struct trace *traces) last_trace = -1; /* If we are partitioning hot/cold basic blocks, mark the cold - traces as already connnected, to remove them from consideration + traces as already connected, to remove them from consideration for connection to the hot traces. After the hot traces have all been connected (determined by "unconnected_hot_trace_count"), we will go back and connect the cold traces. */ diff --git a/gcc/c-opts.c b/gcc/c-opts.c index c63913671fb..9acdf6f425e 100644 --- a/gcc/c-opts.c +++ b/gcc/c-opts.c @@ -101,7 +101,7 @@ static size_t deferred_count; /* Number of deferred options scanned for -include. */ static size_t include_cursor; -/* Permit Fotran front-end options. */ +/* Permit Fortran front-end options. */ static bool permit_fortran_options; static void set_Wimplicit (int); diff --git a/gcc/cfglayout.c b/gcc/cfglayout.c index c5b89ac92ad..e62c60ab83f 100644 --- a/gcc/cfglayout.c +++ b/gcc/cfglayout.c @@ -1172,7 +1172,7 @@ cfg_layout_initialize_rbi (basic_block bb) memset (bb->rbi, 0, sizeof (struct reorder_block_def)); } -/* Main entry point to this module - initialize the datastructures for +/* Main entry point to this module - initialize the data structures for CFG layout changes. It keeps LOOPS up-to-date if not null. */ void diff --git a/gcc/cgraph.c b/gcc/cgraph.c index 0766a5dcb6b..c1e66f933a6 100644 --- a/gcc/cgraph.c +++ b/gcc/cgraph.c @@ -50,9 +50,9 @@ The callgraph: Intraprocedural information: Callgraph is place to store data needed for intraprocedural optimization. - All datastructures are divided into three components: local_info that + All data structures are divided into three components: local_info that is produced while analyzing the function, global_info that is result - of global walkking of the callgraph on the end of compilation and + of global walking of the callgraph on the end of compilation and rtl_info used by RTL backend to propagate data from already compiled functions to their callers. @@ -60,11 +60,11 @@ The callgraph: The function inlining information is decided in advance and maintained in the callgraph as so called inline plan. - For each inlined call, the calle's node is clonned to represent the + For each inlined call, the callee's node is cloned to represent the new function copy produced by inlininer. - Each inlined call gets unque corresponding clone node of the callee - and the datastructure is updated while inlining is performed, so - the clones are elliminated and their callee edges redirected to the + Each inlined call gets a unique corresponding clone node of the callee + and the data structure is updated while inlining is performed, so + the clones are eliminated and their callee edges redirected to the caller. Each edge has "inline_failed" field. When the field is set to NULL, @@ -100,7 +100,7 @@ The varpool data structure: static GTY((param_is (struct cgraph_node))) htab_t cgraph_hash; /* We destructively update callgraph during inlining and thus we need to - keep information on whether inlining happend separately. */ + keep information on whether inlining happened separately. */ htab_t cgraph_inline_hash; /* The linked list of cgraph nodes. */ @@ -152,7 +152,7 @@ eq_node (const void *p1, const void *p2) (tree) p2); } -/* Allocate new callgraph node and insert it into basic datastructures. */ +/* Allocate new callgraph node and insert it into basic data structures. */ static struct cgraph_node * cgraph_create_node (void) { diff --git a/gcc/cgraphunit.c b/gcc/cgraphunit.c index cbe468e2a9e..156c924bca1 100644 --- a/gcc/cgraphunit.c +++ b/gcc/cgraphunit.c @@ -36,7 +36,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA - cgraph_varpool_finalize_variable - This function has same behaviour as the above but is used for static + This function has same behavior as the above but is used for static variables. - cgraph_finalize_compilation_unit @@ -324,7 +324,7 @@ cgraph_finalize_function (tree decl, bool nested) if (node->output) abort (); - /* Reset our datastructures so we can analyze the function again. */ + /* Reset our data structures so we can analyze the function again. */ memset (&node->local, 0, sizeof (node->local)); memset (&node->global, 0, sizeof (node->global)); memset (&node->rtl, 0, sizeof (node->rtl)); @@ -1022,7 +1022,7 @@ cgraph_clone_inlined_nodes (struct cgraph_edge *e, bool duplicate) { struct cgraph_node *n; - /* We may elliminate the need for out-of-line copy to be output. In that + /* We may eliminate the need for out-of-line copy to be output. In that case just go ahead and re-use it. */ if (!e->callee->callers->next_caller && (!e->callee->needed || DECL_EXTERNAL (e->callee->decl)) @@ -1348,7 +1348,7 @@ cgraph_decide_inlining_of_small_functions (void) } /* Decide on the inlining. We do so in the topological order to avoid - expenses on updating datastructures. */ + expenses on updating data structures. */ static void cgraph_decide_inlining (void) @@ -1491,7 +1491,7 @@ cgraph_decide_inlining (void) } /* Decide on the inlining. We do so in the topological order to avoid - expenses on updating datastructures. */ + expenses on updating data structures. */ static void cgraph_decide_inlining_incrementally (struct cgraph_node *node) @@ -1561,7 +1561,7 @@ cgraph_expand_all_functions (void) if (order_pos != cgraph_n_nodes) abort (); - /* Garbage collector may remove inline clones we elliminate during + /* Garbage collector may remove inline clones we eliminate during optimization. So we must be sure to not reference them. */ for (i = 0; i < order_pos; i++) if (order[i]->output) diff --git a/gcc/config/alpha/ev4.md b/gcc/config/alpha/ev4.md index cee3ae608ee..5056fa1277a 100644 --- a/gcc/config/alpha/ev4.md +++ b/gcc/config/alpha/ev4.md @@ -98,7 +98,7 @@ "ev4_ist" "store_data_bypass_p") -; Multiplies use a non-piplined imul unit. Also, "no [ebox] insn can +; Multiplies use a non-pipelined imul unit. Also, "no [ebox] insn can ; be issued exactly three cycles before an integer multiply completes". (define_insn_reservation "ev4_imulsi" 21 diff --git a/gcc/config/alpha/ev5.md b/gcc/config/alpha/ev5.md index 20757e15159..ece25d7e961 100644 --- a/gcc/config/alpha/ev5.md +++ b/gcc/config/alpha/ev5.md @@ -18,7 +18,7 @@ ;; the Free Software Foundation, 59 Temple Place - Suite 330, ;; Boston, MA 02111-1307, USA. -;; EV5 has two asymetric integer units, E0 and E1, plus separate +;; EV5 has two asymmetric integer units, E0 and E1, plus separate ;; FP add and multiply units. (define_automaton "ev5_0,ev5_1") @@ -97,7 +97,7 @@ ; Conditional move and branch can issue the same cycle as the test. (define_bypass 0 "ev5_ilogcmp" "ev5_ibr,ev5_cmov" "if_test_bypass_p") -; Multiplies use a non-piplined imul unit. Also, "no insn can be issued +; Multiplies use a non-pipelined imul unit. Also, "no insn can be issued ; to E0 exactly two cycles before an integer multiply completes". (define_insn_reservation "ev5_imull" 8 @@ -136,7 +136,7 @@ (define_bypass 13 "ev5_imulq" "ev5_imull,ev5_imulq,ev5_imulh") (define_bypass 15 "ev5_imulh" "ev5_imull,ev5_imulq,ev5_imulh") -; Similarly for the FPU we have two asymetric units. +; Similarly for the FPU we have two asymmetric units. (define_insn_reservation "ev5_fadd" 4 (and (eq_attr "cpu" "ev5") diff --git a/gcc/config/alpha/ev6.md b/gcc/config/alpha/ev6.md index 23a09b053a3..561ca709d5d 100644 --- a/gcc/config/alpha/ev6.md +++ b/gcc/config/alpha/ev6.md @@ -22,7 +22,7 @@ ; expected to help over-much, but a precise description can be important ; for software pipelining. ; -; EV6 has two symmetric pairs ("clusters") of two asymetric integer +; EV6 has two symmetric pairs ("clusters") of two asymmetric integer ; units ("upper" and "lower"), yielding pipe names U0, U1, L0, L1. ; ; ??? The clusters have independent register files that are re-synced diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index a8007c91d8f..02864fb28ea 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -7875,7 +7875,7 @@ print_multi_reg (FILE *stream, const char *instr, int reg, int mask) /* Add a ^ character for the 26-bit ABI, but only if we were loading the PC. Otherwise we would generate an UNPREDICTABLE instruction. - Strictly speaking the instruction would be unpredicatble only if + Strictly speaking the instruction would be unpredictable only if we were writing back the base register as well, but since we never want to generate an LDM type 2 instruction (register bank switching) which is what you get if the PC is not being loaded, we do not need diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c index 7500526d435..0dad6a4c97c 100644 --- a/gcc/config/c4x/c4x.c +++ b/gcc/config/c4x/c4x.c @@ -1244,7 +1244,7 @@ c4x_emit_move_sequence (rtx *operands, enum machine_mode mode) && dp_reg_operand (XEXP (op1, 0), mode)) { /* expand_increment will sometimes create a LO_SUM immediate - address. Undo this sillyness. */ + address. Undo this silliness. */ op1 = XEXP (op1, 1); } diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md index 0999adca406..1ea954abdd8 100644 --- a/gcc/config/c4x/c4x.md +++ b/gcc/config/c4x/c4x.md @@ -154,7 +154,7 @@ ; not for 'c'. ; The 'f' constraint is only for float register operands---when -; a register satisying the 'f' constraint is used as a dst operand, +; a register satisfying the 'f' constraint is used as a dst operand, ; the CC gets clobbered (except for LDFcond). ; The ! in front of the 'b' constraint says to GCC to disparage the @@ -190,7 +190,7 @@ ; didn't allow it to move the CC around. ; Note that fundamental operations, such as moves, must not clobber the -; CC. Thus movqi choses a move instruction that doesn't clobber the CC. +; CC. Thus movqi chooses a move instruction that doesn't clobber the CC. ; If GCC wants to combine a move with a compare, it is smart enough to ; chose the move instruction that sets the CC. diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index 86795af91ff..a975f0b8509 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -2947,7 +2947,7 @@ cris_split_movdx (rtx *operands) int reverse = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0); - /* The original code imples that we can't do + /* The original code implies that we can't do move.x [rN+],rM move.x [rN],rM+1 when rN is dead, because of REG_NOTES damage. That is consistent with what I've seen, so don't try it. diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index 7b028e062e9..a4a08fe3151 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -337,7 +337,7 @@ extern int target_flags; /* Whether or not to work around multiplication instruction hardware bug when generating code for models where it may be present. From the trouble report for Etrax 100 LX: "A multiply operation may cause - incorrect cache behaviour under some specific circumstances. The + incorrect cache behavior under some specific circumstances. The problem can occur if the instruction following the multiply instruction causes a cache miss, and multiply operand 1 (source operand) bits [31:27] matches the logical mapping of the mode register address diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h index c7459f83205..81b5f1f9bc5 100644 --- a/gcc/config/fr30/fr30.h +++ b/gcc/config/fr30/fr30.h @@ -1208,7 +1208,7 @@ extern struct rtx_def * fr30_compare_op0; extern struct rtx_def * fr30_compare_op1; /*}}}*/ -/*{{{ PERDICATE_CODES. */ +/*{{{ PREDICATE_CODES. */ #define PREDICATE_CODES \ { "stack_add_operand", { CONST_INT }}, \ diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c index 242dfcde9ce..d5808bfa7ac 100644 --- a/gcc/config/frv/frv.c +++ b/gcc/config/frv/frv.c @@ -6627,7 +6627,7 @@ frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) } -/* Internal function to add a potenial insn to the list of insns to be inserted +/* Internal function to add a potential insn to the list of insns to be inserted if the conditional execution conversion is successful. */ static void diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h index d1f308282fa..1e892102994 100644 --- a/gcc/config/frv/frv.h +++ b/gcc/config/frv/frv.h @@ -931,7 +931,7 @@ extern int target_flags; #define LAST_ARG_REGNUM (FIRST_ARG_REGNUM + FRV_NUM_ARG_REGS - 1) /* Registers used by the exception handling functions. These should be - registers that are not otherwised used by the calling sequence. */ + registers that are not otherwise used by the calling sequence. */ #define FIRST_EH_REGNUM 14 #define LAST_EH_REGNUM 15 diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md index ef2b49d128c..20170bd4123 100644 --- a/gcc/config/frv/frv.md +++ b/gcc/config/frv/frv.md @@ -2788,7 +2788,7 @@ [(set_attr "length" "8") (set_attr "type" "multi")]) -;; Patterns for addsi3/subdi3 after spliting +;; Patterns for addsi3/subdi3 after splitting (define_insn "adddi3_lower" [(set (match_operand:SI 0 "integer_register_operand" "=d") (plus:SI (match_operand:SI 1 "integer_register_operand" "d") diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c index 6bf3bfcfa68..789bb00c537 100644 --- a/gcc/config/h8300/h8300.c +++ b/gcc/config/h8300/h8300.c @@ -4671,7 +4671,7 @@ same_cmp_following_p (rtx i1) } /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes - (or pops) N registers. OPERANDS are asssumed to be an array of + (or pops) N registers. OPERANDS are assumed to be an array of registers. */ int diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 615f2eeec49..5a6832ded25 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -15817,7 +15817,7 @@ ix86_expand_vector_init (rtx target, rtx vals) } /* ... values where only first field is non-constant are best loaded - from the pool and overwriten via move later. */ + from the pool and overwritten via move later. */ if (!i) { rtx op = simplify_gen_subreg (mode, XVECEXP (vals, 0, 0), diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3a87e712234..e258559d188 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -14937,7 +14937,7 @@ ;; With sincos pattern defined, sin and cos builtin function will be ;; expanded to sincos pattern with one of its outputs left unused. ;; Cse pass will detected, if two sincos patterns can be combined, -;; otherwise sincos pattern will be splitted back to sin or cos pattern, +;; otherwise sincos pattern will be split back to sin or cos pattern, ;; depending on the unused output. (define_insn "sincosdf3" diff --git a/gcc/config/i386/winnt.c b/gcc/config/i386/winnt.c index c4326f01a28..b97810a67ed 100644 --- a/gcc/config/i386/winnt.c +++ b/gcc/config/i386/winnt.c @@ -672,7 +672,7 @@ i386_pe_section_type_flags (tree decl, const char *name, int reloc) unsigned int **slot; /* The names we put in the hashtable will always be the unique - versions gived to us by the stringtable, so we can just use + versions given to us by the stringtable, so we can just use their addresses as the keys. */ if (!htab) htab = htab_create (31, htab_hash_pointer, htab_eq_pointer, NULL); diff --git a/gcc/config/ia64/itanium2.md b/gcc/config/ia64/itanium2.md index 0cdb0701346..6e71f5b0f9a 100644 --- a/gcc/config/ia64/itanium2.md +++ b/gcc/config/ia64/itanium2.md @@ -484,7 +484,7 @@ (define_reservation "2_M_only_um01" "2_M0_only_um01|2_M1_only_um01") ;; I instruction is dispersed to the lowest numbered I unit -;; not already in use. Remeber about possible splitting. +;; not already in use. Remember about possible splitting. (define_reservation "2_I0" "2_0mi.i+2_ui0|2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0\ |2_0mfi.+2_ui0|2_0mi.b+2_ui0|(2_1mi.i|2_1mi.b)+(2_ui0|2_ui1)\ @@ -1335,7 +1335,7 @@ +(2b_um2|2b_um3)") ;; I instruction is dispersed to the lowest numbered I unit -;; not already in use. Remeber about possible splitting. +;; not already in use. Remember about possible splitting. (define_reservation "2b_I" "2b_0mi.i+2_2+2b_ui0|2b_0mii.+2_3+(2b_ui0|2b_ui1)|2b_0mmi.+2_3+2b_ui0\ |2b_0mfi.+2_3+2b_ui0|2b_0mi.b+2_2+2b_ui0\ diff --git a/gcc/config/ip2k/ip2k.c b/gcc/config/ip2k/ip2k.c index c6fd0d1b968..05ccb614c4f 100644 --- a/gcc/config/ip2k/ip2k.c +++ b/gcc/config/ip2k/ip2k.c @@ -2730,7 +2730,7 @@ ip2k_gen_unsigned_comp_branch (rtx insn, enum rtx_code code, rtx label) case GTU: if (imm_sub) { - /* > 0xffffffffffffffff never suceeds! */ + /* > 0xffffffffffffffff never succeeds! */ if (((const_high & 0xffffffff) != 0xffffffff) || ((const_low & 0xffffffff) != 0xffffffff)) { @@ -2948,7 +2948,7 @@ ip2k_gen_unsigned_comp_branch (rtx insn, enum rtx_code code, rtx label) if (((const_high & 0xffffffff) == 0xffffffff) && ((const_low & 0xffffffff) == 0xffffffff)) { - /* <= 0xffffffffffffffff always suceeds. */ + /* <= 0xffffffffffffffff always succeeds. */ OUT_AS1 (page, %2); OUT_AS1 (jmp, %2); } diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index bbb664ec0b9..ccb2b3fbab8 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -4762,7 +4762,7 @@ override_options (void) (1) The value of an R_MIPS_GOT16 relocation depends on whether the symbol is local or global. We therefore need to know - a symbol's binding before refering to it using %got(). + a symbol's binding before referring to it using %got(). (2) R_MIPS_CALL16 can only be applied to global symbols. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index e678ba98449..3c3936d8533 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -2076,7 +2076,7 @@ extern enum reg_class mips_char_to_class[256]; `T' is for constant move_operands that cannot be safely loaded into $25. `U' is for constant move_operands that can be safely loaded into $25. `W' is for memory references that are based on a member of BASE_REG_CLASS. - This is true for all non-mips16 references (although it can somtimes + This is true for all non-mips16 references (although it can sometimes be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes stack and constant-pool references. */ diff --git a/gcc/config/mips/sr71k.md b/gcc/config/mips/sr71k.md index ef7e650da77..f1ce973b335 100644 --- a/gcc/config/mips/sr71k.md +++ b/gcc/config/mips/sr71k.md @@ -17,7 +17,7 @@ ;; contrived to support published timings. ;; ;; Reference: -;; "SR3 Microporocessor Specification, System development information," +;; "SR3 Microprocessor Specification, System development information," ;; Revision 1.0, 13 December 2000. ;; ;; diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index d9dea93304d..d4a286d4d8f 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -8419,7 +8419,7 @@ pa_reorg (void) markers disables output of the branch table to readonly memory, and any alignment directives that might be needed. Possibly, the begin_brtab insn should be output before the label for the - table. This doesn matter at the moment since the tables are + table. This doesn't matter at the moment since the tables are always output in the text section. */ for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) { diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 63fc3e57c9a..ed277ad4e85 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -5219,7 +5219,7 @@ s390_return_addr_rtx (int count, rtx frame) return gen_rtx_MEM (Pmode, addr); } -/* Find first call clobbered register unsused in a function. +/* Find first call clobbered register unused in a function. This could be used as base register in a leaf function or for holding the return address before epilogue. */ diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 66a7da47e1e..ed4b714ad89 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -338,7 +338,7 @@ static tree sh_build_builtin_va_list (void); TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic scheduler; it is called inside the sched_init function just after find_insn_reg_weights function call. It is used to calculate the SImode - and SFmode weights of insns of basic blocks; much similiar to what + and SFmode weights of insns of basic blocks; much similar to what find_insn_reg_weights does. TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook. diff --git a/gcc/cppfiles.c b/gcc/cppfiles.c index bdfaa3f9ac6..41657ce91ff 100644 --- a/gcc/cppfiles.c +++ b/gcc/cppfiles.c @@ -382,7 +382,7 @@ _cpp_find_failed (_cpp_file *file) /* Given a filename FNAME search for such a file in the include path starting from START_DIR. If FNAME is the empty string it is - interpreted as STDIN if START_DIR is PFILE->no_seach_path. + interpreted as STDIN if START_DIR is PFILE->no_search_path. If the file is not found in the file cache fall back to the O/S and add the result to our cache. @@ -1342,7 +1342,7 @@ cpp_get_prev (cpp_buffer *b) return b->prev; } -/* This datastructure holds the list of header files that were seen +/* This data structure holds the list of header files that were seen while the PCH was being built. The 'entries' field is kept sorted in memcmp() order; yes, this means that on little-endian systems, it's sorted initially by the least-significant byte of 'size', but diff --git a/gcc/fold-const.c b/gcc/fold-const.c index e2a1ffb096f..1aed785c31d 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -8875,7 +8875,7 @@ tree_expr_nonzero_p (tree t) { tree type = TREE_TYPE (t); - /* Doing something usefull for floating point would need more work. */ + /* Doing something useful for floating point would need more work. */ if (!INTEGRAL_TYPE_P (type) && !POINTER_TYPE_P (type)) return false; diff --git a/gcc/ggc-zone.c b/gcc/ggc-zone.c index 51fb1f938cf..afdead25b16 100644 --- a/gcc/ggc-zone.c +++ b/gcc/ggc-zone.c @@ -1293,7 +1293,7 @@ struct ggc_pch_data size_t written; }; -/* Initialize the PCH datastructure. */ +/* Initialize the PCH data structure. */ struct ggc_pch_data * init_ggc_pch (void) diff --git a/gcc/loop-doloop.c b/gcc/loop-doloop.c index 0396957c0f1..fa6b55b3cfa 100644 --- a/gcc/loop-doloop.c +++ b/gcc/loop-doloop.c @@ -129,7 +129,7 @@ doloop_condition_get (rtx pattern) return condition; /* ??? If a machine uses a funny comparison, we could return a - canonicalised form here. */ + canonicalized form here. */ return 0; } diff --git a/gcc/optabs.c b/gcc/optabs.c index b32315ba463..8d2a232a469 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -1089,7 +1089,7 @@ expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, /* If TARGET is the same as one of the operands, the REG_EQUAL note won't be accurate, so use a new target. Do this also if target is not a REG, first because having a register instead may open optimization - oportunities, and second because if target and op0 happen to be MEMs + opportunities, and second because if target and op0 happen to be MEMs designating the same location, we would risk clobbering it too early in the code sequence we generate below. */ if (target == 0 || target == op0 || target == op1 || ! REG_P (target)) diff --git a/gcc/reg-stack.c b/gcc/reg-stack.c index 6d101841993..8464ab43bc6 100644 --- a/gcc/reg-stack.c +++ b/gcc/reg-stack.c @@ -3045,7 +3045,7 @@ convert_regs (FILE *file) /* ??? Future: process inner loops first, and give them arbitrary initial stacks which emit_swap_insn can modify. This ought to - prevent double fxch that aften appears at the head of a loop. */ + prevent double fxch that often appears at the head of a loop. */ /* Process all blocks reachable from all entry points. */ for (e = ENTRY_BLOCK_PTR->succ; e ; e = e->succ_next) diff --git a/gcc/varasm.c b/gcc/varasm.c index e94187f2d1d..13f1191a308 100644 --- a/gcc/varasm.c +++ b/gcc/varasm.c @@ -236,7 +236,7 @@ unlikely_text_section (void) current_function_name ()); unlikely_section_label_printed = true; - /* Make sure that we have approprate alignment for instructions + /* Make sure that we have appropriate alignment for instructions in this section. */ assemble_align (FUNCTION_BOUNDARY); }