From: lkcl <lkcl@web>
Date: Sat, 19 Dec 2020 15:38:06 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1190
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ae5ca48fb86e4183fddeb3e27140dc9e7a4fc2f;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 17aaf6518..42ce6e156 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -29,11 +29,11 @@ Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise
     // instruction fields:
     rd = get_rt_field();         // bits 6..10
     ra = get_ra_field();         // bits 11..15
-    // add one. MVL/VL=1..64 not 0..63
-    vlimmed = get_immed_field()+1; //  16..22
     vs = get_vs_field();         // bit 24
     ms = get_ms_field();         // bit 25
     Rc = get_Rc_field();         // bit 31
+    // add one. MVL/VL=1..64 not 0..63
+    vlimmed = get_immed_field()+1; //  16..22
 
     // set VL (or not).
     // 3 options: from SPR, from immed, from ra