From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 20 Jul 2018 05:50:27 +0000 (+0100)
Subject: add axi slave definitions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1af46226a7760d44e50d61b71bc1e73da161cc93;p=pinmux.git

add axi slave definitions
---

diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv
index c5824b2..33fcbe8 100644
--- a/src/bsv/bsv_lib/slow_peripherals_template.bsv
+++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv
@@ -10,6 +10,9 @@ package slow_peripherals;
 	`include "instance_defines.bsv"
     /* ==== define the AXI Addresses ==== */
 {2}
+    /*====== AXI4 Lite slave declarations =======*/
+
+{3}
 	/*===========================*/
 	/*=== package imports ===*/
 	import Clocks::*;
diff --git a/src/bsv/interface_decl.py b/src/bsv/interface_decl.py
index 0588164..d28b90e 100644
--- a/src/bsv/interface_decl.py
+++ b/src/bsv/interface_decl.py
@@ -9,6 +9,7 @@ from bsv.wire_def import generic_io  # special case
 from bsv.wire_def import muxwire  # special case
 from ifacebase import InterfacesBase
 from bsv.peripheral_gen import PFactory
+from bsv.peripheral_gen import axi_slave_declarations
 slowfactory = PFactory()
 
 
@@ -273,6 +274,11 @@ class Interface(object):
             return ('', 0)
         return self.slow.axi_reg_def(start, self.ifacename, count)
 
+    def axi_slave_idx(self, start, count):
+        if not self.slow:
+            return ('', 0)
+        return self.slow.axi_slave_idx(start, self.ifacename, count)
+
 
 class MuxInterface(Interface):
 
@@ -359,6 +365,19 @@ class Interfaces(InterfacesBase):
                 start += offs
         return '\n'.join(list(filter(None, ret)))
 
+    def axi_slave_idx(self, *args):
+        ret = []
+        start = 0
+        for (name, count) in self.ifacecount:
+            for i in range(count):
+                (rdef, offs) = self.data[name].axi_slave_idx(start, i)
+                print ("ifc", name, rdef, offs)
+                ret.append(rdef)
+                start += offs
+        ret.append("typedef %d LastGen_slave_num" % (start-1))
+        decls = '\n'.join(list(filter(None, ret)))
+        return axi_slave_declarations.format(decls)
+
 
 # ========= Interface declarations ================ #
 
diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index 5e4a18b..d609d34 100644
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -22,7 +22,7 @@ class PBase(object):
 
     def axi_slave_idx(self, idx, name, ifacenum):
         name = name.upper()
-        return "typedef {0} {1}{2}_slave_num;".format(idx, name, ifacenum)
+        return ("typedef {0} {1}{2}_slave_num;".format(idx, name, ifacenum), 1)
 
 
 class uart(PBase):
@@ -96,6 +96,28 @@ class gpio(PBase):
     def num_axi_regs32(self):
         return 2
 
+    def axi_slave_idx(self, idx, name, ifacenum):
+        """ generates AXI slave number definition, except
+            GPIO also has a muxer per bank
+        """
+        name = name.upper()
+        (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
+        (ret2, x) = PBase.axi_slave_idx(self, idx, "mux", ifacenum)
+        return ("%s\n%s" % (ret, ret2), 2)
+
+
+axi_slave_declarations = """\
+typedef  0  SlowMaster;
+{0}
+typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
+              CLINT_slave_num;
+typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
+              Plic_slave_num;
+typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
+              AxiExp1_slave_num;
+typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
+"""
+
 
 class PFactory(object):
     def getcls(self, name):
diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 560704e..8098860 100644
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -102,8 +102,9 @@ def write_slow(slow, template, p, ifaces):
     imports = ifaces.slowimport()
     ifdecl = ifaces.slowifdecl()
     regdef = ifaces.axi_reg_def()
+    slavedecl = ifaces.axi_slave_idx()
     with open(slow, "w") as bsv_file:
-        bsv_file.write(template.format(imports, ifdecl, regdef))
+        bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl))
 
 
 def write_bus(bus, p, ifaces):