From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Feb 2022 13:45:22 +0000 (+0000)
Subject: fix missing uart_top (ordering of read_verilog is now important)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1af7aae227754c895f026a45726f4cb15dc308cb;p=microwatt.git

fix missing uart_top (ordering of read_verilog is now important)
---

diff --git a/Makefile b/Makefile
index 192648c..88cbdbe 100644
--- a/Makefile
+++ b/Makefile
@@ -213,7 +213,7 @@ _fpga_files = fpga/soc_reset.vhdl \
 	nonrandom.vhdl
 
 # use an alternative core (in verilog)
-EXTERNAL_CORE=false
+EXTERNAL_CORE=true
 ifeq ($(EXTERNAL_CORE),false)
     fpga_files = $(_fpga_files) $(_soc_files) $(core_files)
     synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
@@ -230,7 +230,11 @@ GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE
 	-gEXTERNAL_CORE=$(EXTERNAL_CORE)
 
 microwatt.json: $(synth_files) $(RAM_INIT_FILE)
-	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)" $(uart_files)
+	$(YOSYS) -m $(GHDLSYNTH) -p \
+		"ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) \
+		$(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; \
+		read_verilog $(uart_files) $(soc_extra_v); \
+		synth_ecp5 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"
 
 microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"