From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 22:31:48 +0000 (-0700)
Subject: Merge branch 'eddie/xilinx_srl' into xaig_arrival
X-Git-Tag: working-ls180~1075^2^2~31
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b08f861b6f95dba561ec48f71d3ab5bc18f64f2;p=yosys.git

Merge branch 'eddie/xilinx_srl' into xaig_arrival
---

1b08f861b6f95dba561ec48f71d3ab5bc18f64f2
diff --cc techlibs/xilinx/synth_xilinx.cc
index db8c9fa31,3760a1129..bfc0ac2bf
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -448,13 -448,17 +450,18 @@@ struct SynthXilinxPass : public ScriptP
  			// This shregmap call infers fixed length shift registers after abc
  			//   has performed any necessary retiming
  			if (!nosrl || help_mode)
- 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
- 			std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/ff_map.v";
- 			if (abc9)
+ 				run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
 -
+ 			std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
+ 			if (help_mode)
 -					techmap_args += " [-map +/xilinx/ff_map.v]";
 -			else if (!abc9)
 -					techmap_args += " -map +/xilinx/ff_map.v";
++				techmap_args += " [-map +/xilinx/ff_map.v]";
++			else if (abc9)
 +				techmap_args += " -map +/xilinx/abc_unmap.v";
++			else
++				techmap_args += " -map +/xilinx/ff_map.v";
  			run("techmap " + techmap_args);
- 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
- 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 -			if (!abc9)
++			if (!abc9 || help_mode)
+ 				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+ 						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "(without '-abc9' only)");
  			run("clean");
  		}