From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jun 2020 14:30:02 +0000 (+0100)
Subject: wark-wark, do not & rs[0] into carry-out from rotator
X-Git-Tag: div_pipeline~496
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b1703273d54ba3ecd09fd7cd7f17dc7fadfdb1c;p=soc.git

wark-wark, do not & rs[0] into carry-out from rotator
---

diff --git a/src/soc/fu/shift_rot/rotator.py b/src/soc/fu/shift_rot/rotator.py
index b5dc80ee..8a20b0ba 100644
--- a/src/soc/fu/shift_rot/rotator.py
+++ b/src/soc/fu/shift_rot/rotator.py
@@ -156,7 +156,7 @@ class Rotator(Elaboratable):
             with m.Case(0b11):
                 comb += self.result_o.eq(rot | ~mr)
                 # Generate carry output for arithmetic shift right of -ve value
-                comb += self.carry_out_o.eq((rs & ~ml).bool() & rs[0])
+                comb += self.carry_out_o.eq((rs & ~ml).bool())
 
         return m