From: Michael Eager Date: Fri, 19 Mar 2004 23:12:10 +0000 (+0000) Subject: atomicity.h: Prevent reg loads between LL and SC instructions. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b1a632b4dd80cc7c688bab50c38c66632f8d636;p=gcc.git atomicity.h: Prevent reg loads between LL and SC instructions. 2004-03-19 Michael Eager * config/cpu/mips/atomicity.h: Prevent reg loads between LL and SC instructions. From-SVN: r79711 --- diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index 0f8d8f03675..fe893b043dc 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,8 @@ +2004-03-19 Michael Eager + + * config/cpu/mips/atomicity.h: Prevent reg loads between LL and + SC instructions. + 2004-03-19 Paolo Carlini * testsuite/22_locale/num_get/get/char/11.cc: Remove redundant diff --git a/libstdc++-v3/config/cpu/mips/atomicity.h b/libstdc++-v3/config/cpu/mips/atomicity.h index 087134289de..ecfb6968594 100644 --- a/libstdc++-v3/config/cpu/mips/atomicity.h +++ b/libstdc++-v3/config/cpu/mips/atomicity.h @@ -44,14 +44,15 @@ namespace __gnu_cxx #if _MIPS_SIM == _ABIO32 ".set mips2\n\t" #endif - "ll %0,%3\n\t" - "addu %1,%4,%0\n\t" - "sc %1,%2\n\t" + "ll %0,0(%2)\n\t" + "addu %1,%3,%0\n\t" + "sc %1,0(%2)\n\t" ".set pop\n\t" "beqz %1,1b\n\t" "/* End exchange & add */" - : "=&r"(__result), "=&r"(__tmp), "=m"(*__mem) - : "m" (*__mem), "r"(__val)); + : "=&r"(__result), "=&r"(__tmp) + : "r"(__mem), "r"(__val) + : "memory" ); return __result; } @@ -69,13 +70,14 @@ namespace __gnu_cxx #if _MIPS_SIM == _ABIO32 ".set mips2\n\t" #endif - "ll %0,%2\n\t" - "addu %0,%3,%0\n\t" - "sc %0,%1\n\t" + "ll %0,0(%1)\n\t" + "addu %0,%2,%0\n\t" + "sc %0,0(%1)\n\t" ".set pop\n\t" "beqz %0,1b\n\t" "/* End atomic add */" - : "=&r"(__result), "=m"(*__mem) - : "m" (*__mem), "r"(__val)); + : "=&r"(__result) + : "r"(__mem), "r"(__val) + : "memory" ); } } // namespace __gnu_cxx