From: lkcl <lkcl@web>
Date: Tue, 7 Jun 2022 18:35:21 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1913
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b1e39978fea4429f7999b77367e4921952751e7;p=libreriscv.git

---

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index 6299b3eb5..f6546b9ca 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -4,9 +4,10 @@
 
 The purpose of the Compliancy Levels is to provide a documented
 stable base for implementors to achieve software interoperability
-without requiring a high and unnecessary hardware cost.  The bare
+without requiring a high and unnecessary hardware cost unrelated
+to their needs. The bare
 minimum requirement, particularly suited for Ultra-embedded, requires
-just two instructions, reservation of SPRs, and the rest may entirely
+just one instruction, reservation of SPRs, and the rest may entirely
 be Soft-emulated by raising Illegal Instruction traps.  At the other
 end of the spectrum is the full REMAP Structure Packing suitable
 for traditional Vector Processing workloads and High-performance
@@ -24,7 +25,8 @@ Summary of Compliancy Levels, each Level includes all lower levels:
 * **Embedded**: `svstep` instruction,
   and support for Hardware for-looping
   in both Horizontal-First and Vertical-First Mode as well as Predication
-  (Single and Twin)
+  (Single and Twin) for the GPRs r3, r10 and r30.  CR-Field-based
+  Predicates, if used, may still raise illegal instruction trap.
 * **DSP/VPU**: 128 registers, all SV Branch instructions,
   crweird instructions, element-width
   overrides, and all Modes (Saturation, Fail-First, Predicate-Result,
@@ -72,3 +74,27 @@ Illegal Instruction Trap **must** be raised on:
 Implementors are free and clear to implement any other features of
 SVP64 however only by meeting all of the mandatory requirements above
 will Compliance with the Ultra-Embedded Level be achieved.
+
+# Embedded Level
+
+This level is more suitable for Hardware implementations where performance and power saving begins to matter.  A second instruction, `svstep`, used
+by Vertical-First Mode, is required, as is hardware-level looping in
+Horizontal-First Mode. Illegal Instruction trap may not be called to
+emulate `svstep`.
+
+At the bare minimum, Twin and Single Predication must be supported for
+at least the GPRs r3, r10 and r30.  CR Field Predication may also be
+supported in hardware but only by also increasing the number of CR Fields
+to 128.
+
+Another important aspect is that when Rc=1 is set, CR Field Vector co-results
+are produced. Should these exceed CR7 (CR8-CR127) and the number of CR Fields
+has not been increased to 128 then an Illegal Instruction Trap must be
+raised.  In practical terms, to avoid this scenario, MAXVL should not
+exceed 8 for Arithmetic or Logical operations when Rc=1.
+
+Zeroing on source and destination for Predicates
+must also be supported (sz, dz) however
+all other Modes (Saturation, Fail-First, Predicate-Result,
+Iteration/Reduction) are entirely optional. Implementation of Element-Width
+Overrides is also optional.