From: lkcl <lkcl@web>
Date: Fri, 18 Jun 2021 12:02:45 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~745
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b2934add724c4b6075dde6d3d0617d3f6ad3857;p=libreriscv.git

---

diff --git a/openpower/sv/propagation.mdwn b/openpower/sv/propagation.mdwn
index f45afba21..16bf2b884 100644
--- a/openpower/sv/propagation.mdwn
+++ b/openpower/sv/propagation.mdwn
@@ -60,6 +60,12 @@ as follows:
 * Starting from bit 32 of the 4th SPR, in batches of 40 bits the Shift
   Registers are stored.
 
+               0            31 32         63
+    SVREMAP0   context 0       context 1
+    SVREMAP1   context 2       context 3
+    SVREMAP2   context 4       context 5
+    SVREMAP3   context 6       
+
 When each LSB is nonzero in any one of the seven Shift Registers
 the corresponding Contexts are looked up and merged (ORed) together.
 Contexts for different purposes however may not be mixed: an illegal