From: Gabe Black Date: Sat, 19 Oct 2019 00:49:45 +0000 (-0700) Subject: fastmodel: Implement port proxies. X-Git-Tag: v19.0.0.0~177 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b48cfd7617e3cd54086121d36ad8364a29f1d90;p=gem5.git fastmodel: Implement port proxies. This plumbing is simple and largely copied from other implementations within gem5. This mechanism should be refactored so that the duplication is unnecessary. Change-Id: Ibcdf759b7fba1d574e8e2ba04249afdd92c6560c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22120 Reviewed-by: Giacomo Travaglini Reviewed-by: Chun-Chen TK Hsu Maintainer: Giacomo Travaglini Tested-by: kokoro --- diff --git a/src/arch/arm/fastmodel/iris/cpu.cc b/src/arch/arm/fastmodel/iris/cpu.cc index 8284d1717..d66cf1dbc 100644 --- a/src/arch/arm/fastmodel/iris/cpu.cc +++ b/src/arch/arm/fastmodel/iris/cpu.cc @@ -78,4 +78,12 @@ BaseCPU::totalInsts() const return count; } +void +BaseCPU::init() +{ + ::BaseCPU::init(); + for (auto *tc: threadContexts) + tc->initMemProxies(tc); +} + } // namespace Iris diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh index ef839784c..0d15fc82a 100644 --- a/src/arch/arm/fastmodel/iris/cpu.hh +++ b/src/arch/arm/fastmodel/iris/cpu.hh @@ -116,6 +116,8 @@ class BaseCPU : public ::BaseCPU periodAttribute->value = clockPeriod(); clockEvent->notify(); } + + void init() override; }; // This class specializes the one above and sets up ThreadContexts based on diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc index 89748957c..00c41ba9c 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/thread_context.cc @@ -31,6 +31,8 @@ #include "iris/detail/IrisCppAdapter.h" #include "iris/detail/IrisObjects.h" +#include "mem/fs_translating_port_proxy.hh" +#include "mem/se_translating_port_proxy.hh" namespace Iris { @@ -291,6 +293,22 @@ ThreadContext::getCurrentInstCount() return count; } +void +ThreadContext::initMemProxies(::ThreadContext *tc) +{ + if (FullSystem) { + assert(!physProxy && !virtProxy); + physProxy.reset(new PortProxy(_cpu->getSendFunctional(), + _cpu->cacheLineSize())); + virtProxy.reset(new FSTranslatingPortProxy(tc)); + } else { + assert(!virtProxy); + virtProxy.reset(new SETranslatingPortProxy( + _cpu->getSendFunctional(), getProcessPtr(), + SETranslatingPortProxy::NextPage)); + } +} + ThreadContext::Status ThreadContext::status() const { diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh index 49b3325e7..8d2070a02 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.hh +++ b/src/arch/arm/fastmodel/iris/thread_context.hh @@ -30,6 +30,8 @@ #ifndef __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__ #define __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__ +#include + #include "cpu/base.hh" #include "cpu/thread_context.hh" #include "iris/IrisInstance.h" @@ -77,6 +79,9 @@ class ThreadContext : public ::ThreadContext std::vector memorySpaces; std::vector translations; + std::unique_ptr virtProxy = nullptr; + std::unique_ptr physProxy = nullptr; + // A queue to keep track of instruction count based events. EventQueue comInstEventQueue; @@ -161,21 +166,11 @@ class ThreadContext : public ::ThreadContext { panic("%s not implemented.", __FUNCTION__); } - PortProxy & - getPhysProxy() override - { - panic("%s not implemented.", __FUNCTION__); - } - PortProxy & - getVirtProxy() override - { - panic("%s not implemented.", __FUNCTION__); - } - void - initMemProxies(::ThreadContext *tc) override - { - panic("%s not implemented.", __FUNCTION__); - } + + PortProxy &getPhysProxy() override { return *physProxy; } + PortProxy &getVirtProxy() override { return *virtProxy; } + void initMemProxies(::ThreadContext *tc) override; + Process * getProcessPtr() override {