From: Christoph Brill Date: Mon, 25 Feb 2008 19:20:59 +0000 (+0100) Subject: [r300] Add more struct names for r300_hw_state X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b51c135fc7bce2a801793139f72de7e57e33cfb;p=mesa.git [r300] Add more struct names for r300_hw_state --- diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index b6d52b8bf23..ae4bc64934d 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -420,10 +420,10 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.cb.cmd[R300_CB_CMD_1] = cmdpacket0(R300_RB3D_COLORPITCH0, 1); ALLOC_STATE(rb3d_dither_ctl, always, 10, 0); r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(R300_RB3D_DITHER_CTL, R300_RB3D_DITHER_CTL_DITHER_MODE_ROUND | R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT); - ALLOC_STATE(unk4E88, always, 2, 0); - r300->hw.unk4E88.cmd[0] = cmdpacket0(R300_RB3D_AARESOLVE_CTL, R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE); - ALLOC_STATE(unk4EA0, always, 3, 0); - r300->hw.unk4EA0.cmd[0] = cmdpacket0(RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); + ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0); + r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(R300_RB3D_AARESOLVE_CTL, R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE); + ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0); r300->hw.zs.cmd[R300_ZS_CMD_0] = cmdpacket0(R300_RB3D_ZSTENCIL_CNTL_0, 3); @@ -432,14 +432,14 @@ void r300InitCmdBuf(r300ContextPtr r300) cmdpacket0(R300_RB3D_ZSTENCIL_FORMAT, 4); ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0); r300->hw.zb.cmd[R300_ZB_CMD_0] = cmdpacket0(R300_RB3D_DEPTHOFFSET, 2); - ALLOC_STATE(unk4F28, always, 2, 0); - r300->hw.unk4F28.cmd[0] = cmdpacket0(ZB_DEPTHCLEARVALUE, 1); + ALLOC_STATE(zb_depthclearvalue, always, 2, 0); + r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(ZB_DEPTHCLEARVALUE, 1); ALLOC_STATE(unk4F30, always, 3, 0); r300->hw.unk4F30.cmd[0] = cmdpacket0(0x4F30, 2); - ALLOC_STATE(unk4F44, always, 2, 0); - r300->hw.unk4F44.cmd[0] = cmdpacket0(ZB_HIZ_OFFSET, 1); - ALLOC_STATE(unk4F54, always, 2, 0); - r300->hw.unk4F54.cmd[0] = cmdpacket0(ZB_HIZ_PITCH, 1); + ALLOC_STATE(zb_hiz_offset, always, 2, 0); + r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(ZB_HIZ_OFFSET, 1); + ALLOC_STATE(zb_hiz_pitch, always, 2, 0); + r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(ZB_HIZ_PITCH, 1); /* VPU only on TCL */ if (has_tcl) { diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 17148929d08..ab0d33b905d 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -499,15 +499,15 @@ struct r300_hw_state { struct r300_state_atom blend_color; /* constant blend color */ struct r300_state_atom cb; /* colorbuffer (4E28) */ struct r300_state_atom rb3d_dither_ctl; /* (4E50) */ - struct r300_state_atom unk4E88; /* (4E88) */ - struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware.. */ + struct r300_state_atom rb3d_aaresolve_ctl; /* (4E88) */ + struct r300_state_atom rb3d_discard_src_pixel_lte_threshold; /* (4E88) I saw it only written on RV350 hardware.. */ struct r300_state_atom zs; /* zstencil control (4F00) */ struct r300_state_atom zstencil_format; struct r300_state_atom zb; /* z buffer (4F20) */ - struct r300_state_atom unk4F28; /* (4F28) */ + struct r300_state_atom zb_depthclearvalue; /* (4F28) */ struct r300_state_atom unk4F30; /* (4F30) */ - struct r300_state_atom unk4F44; /* (4F44) */ - struct r300_state_atom unk4F54; /* (4F54) */ + struct r300_state_atom zb_hiz_offset; /* (4F44) */ + struct r300_state_atom zb_hiz_pitch; /* (4F54) */ struct r300_state_atom vpi; /* vp instructions */ struct r300_state_atom vpp; /* vp parameters */ diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index f9ef8bd3959..5fc1dcbe38b 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1978,10 +1978,10 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_dither_ctl.cmd[8] = 0; r300->hw.rb3d_dither_ctl.cmd[9] = 0; - r300->hw.unk4E88.cmd[1] = 0; + r300->hw.rb3d_aaresolve_ctl.cmd[1] = 0; - r300->hw.unk4EA0.cmd[1] = 0x00000000; - r300->hw.unk4EA0.cmd[2] = 0xffffffff; + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; r300->hw.zb.cmd[R300_ZB_OFFSET] = r300->radeon.radeonScreen->depthOffset + @@ -1997,14 +1997,14 @@ static void r300ResetHwState(r300ContextPtr r300) R300_DEPTH_MICROTILE_ENABLE; } - r300->hw.unk4F28.cmd[1] = 0; + r300->hw.zb_depthclearvalue.cmd[1] = 0; r300->hw.unk4F30.cmd[1] = 0; r300->hw.unk4F30.cmd[2] = 0; - r300->hw.unk4F44.cmd[1] = 0; + r300->hw.zb_hiz_offset.cmd[1] = 0; - r300->hw.unk4F54.cmd[1] = 0; + r300->hw.zb_hiz_pitch.cmd[1] = 0; if (has_tcl) { r300->hw.vps.cmd[R300_VPS_ZERO_0] = 0;