From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 22:23:26 +0000 (-0700)
Subject: Do not sigmap!
X-Git-Tag: working-ls180~881^2^2~223
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b5d2de1d4212bd93f9b0ca0d5173e4c8a4dd4e8;p=yosys.git

Do not sigmap!
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ad2a778fa..d02997da4 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -355,7 +355,7 @@ struct XAigerWriter
 						log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
 
 					if (is_input) {
-						for (auto b : sigmap(c.second)) {
+						for (auto b : c.second) {
 							Wire *w = b.wire;
 							if (!w) continue;
 							if (!w->port_output || !cell_known) {
@@ -381,7 +381,7 @@ struct XAigerWriter
 							}
 						}
 
-						for (auto b : sigmap(c.second)) {
+						for (auto b : c.second) {
 							Wire *w = b.wire;
 							if (!w) continue;
 							input_bits.insert(b);