From: Uros Bizjak Date: Tue, 27 Dec 2016 21:25:09 +0000 (+0100) Subject: i386.c (ix86_secondary_reload): Require QImode intermediate for QImode mask register... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b5d6ccdcfa28302e03b1a69609d8aea1a50e43a;p=gcc.git i386.c (ix86_secondary_reload): Require QImode intermediate for QImode mask register spill only for... * config/i386/i386.c (ix86_secondary_reload): Require QImode intermediate for QImode mask register spill only for !TARGET_AVX512DQ. Always use true_regnum to determine operand regno. From-SVN: r243945 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1f17c9e9df6..a46fed0c221 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-12-27 Uros Bizjak + + * config/i386/i386.c (ix86_secondary_reload): Require QImode + intermediate for mask register spill only for !TARGET_AVX512DQ. + Always use true_regnum to determine operand regno. + 2016-12-27 Sandra Loosemore * doc/cppopts.texi: Delete redundant documentation for -x. Move diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 624f0699e66..eb7356e0a6b 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -39752,24 +39752,19 @@ ix86_secondary_reload (bool in_p, rtx x, reg_class_t rclass, /* QImode spills from non-QI registers require intermediate register on 32bit targets. */ if (mode == QImode - && (MAYBE_MASK_CLASS_P (rclass) - || (!TARGET_64BIT && !in_p - && INTEGER_CLASS_P (rclass) - && MAYBE_NON_Q_CLASS_P (rclass)))) + && ((!TARGET_64BIT && !in_p + && INTEGER_CLASS_P (rclass) + && MAYBE_NON_Q_CLASS_P (rclass)) + || (!TARGET_AVX512DQ + && MAYBE_MASK_CLASS_P (rclass)))) { - int regno; - - if (REG_P (x)) - regno = REGNO (x); - else - regno = -1; - - if (regno >= FIRST_PSEUDO_REGISTER || SUBREG_P (x)) - regno = true_regnum (x); + int regno = true_regnum (x); /* Return Q_REGS if the operand is in memory. */ if (regno == -1) return Q_REGS; + + return NO_REGS; } /* This condition handles corner case where an expression involving