From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 8 Jun 2020 16:48:25 +0000 (+0200)
Subject: Connect dramcore to SoC bus in ECPIX-5 example
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b629cb65999f25bd5664c44181a165c84362ffa;p=gram.git

Connect dramcore to SoC bus in ECPIX-5 example
---

diff --git a/examples/ecpix5.py b/examples/ecpix5.py
index d4251bc..3848436 100644
--- a/examples/ecpix5.py
+++ b/examples/ecpix5.py
@@ -152,7 +152,9 @@ class DDR3SoC(CPUSoC, Elaboratable):
 			geom_settings   = ddrmodule.geom_settings,
 			timing_settings = ddrmodule.timing_settings,
 			clk_freq = clk_freq)
-		#self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
+		self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
+
+		self.dramport = self.dramcore.crossbar.get_port()
 
 		self.memory_map = self._decoder.bus.memory_map