From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Wed, 29 Jul 2020 10:01:50 +0000 (+0200)
Subject: Import utils using the absolute module path
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b6de09bd3d4af33625a389157534954cb4a9062;p=gram.git

Import utils using the absolute module path
---

diff --git a/gram/test/test_common.py b/gram/test/test_common.py
index 385282c..7205478 100644
--- a/gram/test/test_common.py
+++ b/gram/test/test_common.py
@@ -3,7 +3,7 @@ from nmigen import *
 from nmigen.hdl.ast import Past
 
 from gram.common import tXXDController, tFAWController
-from utils import *
+from gram.test.utils import *
 
 class tXXDControllerTestCase(FHDLTestCase):
     def test_formal(self):
diff --git a/gram/test/test_compat.py b/gram/test/test_compat.py
index 679a328..4793472 100644
--- a/gram/test/test_compat.py
+++ b/gram/test/test_compat.py
@@ -4,7 +4,7 @@ from nmigen.hdl.ast import Past
 from nmigen.asserts import Assert, Assume
 
 from gram.compat import *
-from utils import *
+from gram.test.utils import *
 
 class DelayedEnterTestCase(FHDLTestCase):
     def test_sequence(self):
diff --git a/gram/test/test_core_crossbar.py b/gram/test/test_core_crossbar.py
index a2da8aa..7d89f0b 100644
--- a/gram/test/test_core_crossbar.py
+++ b/gram/test/test_core_crossbar.py
@@ -3,7 +3,7 @@ from nmigen.hdl.ast import Sample
 from nmigen.asserts import Assert, Assume
 
 from gram.core.crossbar import _DelayLine
-from utils import *
+from gram.test.utils import *
 
 class DelayLineSpec(Elaboratable):
     def __init__(self, delay):
diff --git a/gram/test/test_core_multiplexer.py b/gram/test/test_core_multiplexer.py
index 4d5c858..0643b02 100644
--- a/gram/test/test_core_multiplexer.py
+++ b/gram/test/test_core_multiplexer.py
@@ -3,7 +3,7 @@ from nmigen import *
 from gram.core.multiplexer import _AntiStarvation, _CommandChooser
 from gram.common import cmd_request_rw_layout
 import gram.stream as stream
-from utils import *
+from gram.test.utils import *
 
 class CommandChooserTestCase(FHDLTestCase):
     def prepare_testbench(self):
diff --git a/gram/test/test_core_refresher.py b/gram/test/test_core_refresher.py
index a968536..7460442 100644
--- a/gram/test/test_core_refresher.py
+++ b/gram/test/test_core_refresher.py
@@ -4,7 +4,7 @@ from nmigen.asserts import Assert, Assume
 
 from gram.core.refresher import RefreshExecuter, RefreshSequencer, RefreshTimer, RefreshPostponer, Refresher
 from gram.compat import *
-from utils import *
+from gram.test.utils import *
 
 class RefreshExecuterTestCase(FHDLTestCase):
     def test_executer(self):
diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py
index 195c917..7016da1 100644
--- a/gram/test/test_dfii.py
+++ b/gram/test/test_dfii.py
@@ -3,7 +3,7 @@ from lambdasoc.periph import Peripheral
 
 from gram.dfii import *
 from gram.phy.dfi import Interface
-from utils import *
+from gram.test.utils import *
 
 # Phase injector CSR addresses
 PI_COMMAND_ADDR = 0x00
diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py
index fae835c..d086b91 100644
--- a/gram/test/test_soc.py
+++ b/gram/test/test_soc.py
@@ -17,7 +17,7 @@ from gram.modules import MT41K256M16
 from gram.frontend.wishbone import gramWishbone
 
 from gram.core.multiplexer import _AntiStarvation
-from utils import *
+from gram.test.utils import *
 
 class DDR3SoC(SoC, Elaboratable):
     def __init__(self, *, clk_freq, dramcore_addr,