From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Jun 2020 20:38:43 +0000 (+0100)
Subject: add test_bc_reg (fails)
X-Git-Tag: div_pipeline~664
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b76f8953887e5a50053cffb9b82a07efe6a2d44;p=soc.git

add test_bc_reg (fails)
---

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index c9e059b4..66020211 100644
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -96,6 +96,23 @@ class BranchTestCase(FHDLTestCase):
                                  initial_sprs=initial_sprs,
                                  initial_cr=cr)
 
+    def test_bc_reg(self):
+        # XXX: bcctr and bcctrl time out (irony: they're counters)
+        #choices = ["bclr", "bclrl", "bctar", "bctarl", "bcctr", "bcctrl"]
+        choices = ["bclr", "bclrl", "bctar", "bctarl", ]
+        for insn in choices:
+            for i in range(20):
+                bh = random.randrange(0, 3)
+                bo = random.choice([0, 2, 8, 10, 16, 18])
+                bi = random.randrange(0, 31)
+                cr = random.randrange(0, (1<<32)-1)
+                ctr = random.randint(0, (1<<32)-1)
+                lst = [f"{insn} {bo}, {bi}, {bh}"]
+                initial_sprs={9: SelectableInt(ctr, 64)}
+                self.run_tst_program(Program(lst),
+                                     initial_sprs=initial_sprs,
+                                     initial_cr=cr)
+
     def test_ilang(self):
         pspec = BranchPipeSpec(id_wid=2)
         alu = BranchBasePipe(pspec)