From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Tue, 9 Jun 2020 12:36:44 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b7f428e270964174d27af4e0b1bd2bb03a43bc2;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
---

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+Date: Tue, 09 Jun 2020 12:36:44 +0000
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
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+Message-ID: <bug-336-13-KojH98huGY@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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