From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 4 Jun 2019 18:56:58 +0000 (-0700)
Subject: Only toposort builtin and abc types
X-Git-Tag: working-ls180~1208^2~201
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b836c93bbaa3c85d4730b0251aed64cdf207422;p=yosys.git

Only toposort builtin and abc types
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 818caebba..4d45bb650 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -181,14 +181,17 @@ struct XAigerWriter
 		for (auto cell : module->cells())
 		{
 			RTLIL::Module* inst_module = module->design->module(cell->type);
-			bool known_type = yosys_celltypes.cell_known(cell->type);
+			bool builtin_type = yosys_celltypes.cell_known(cell->type);
+			bool abc_type = inst_module && inst_module->attributes.count("\\abc_box_id");
 
 			if (!holes_mode) {
 				toposort.node(cell->name);
-				for (const auto &conn : cell->connections())
-				{
+				for (const auto &conn : cell->connections()) {
+					if (!builtin_type && !abc_type)
+						continue;
+
 					if (!cell->type.in("$_NOT_", "$_AND_")) {
-						if (known_type) {
+						if (builtin_type) {
 							if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
 								continue;
 							if (cell->type == "$memrd" && conn.first == "\\DATA")
@@ -199,8 +202,8 @@ struct XAigerWriter
 							RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
 							log_assert(inst_module_port);
 
-							if (inst_module_port->attributes.count("\\abc_flop_q"))
-								continue;
+							if (inst_module_port->port_output && inst_module_port->attributes.count("\\abc_flop_q"))
+									continue;
 						}
 					}