From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 04:58:34 +0000 (-0700)
Subject: Clarify
X-Git-Tag: working-ls180~1039^2~68
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b88211ec61d70ee34f9dc21647ebd941d91fcb4;p=yosys.git

Clarify
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index adc09a6e4..abd145723 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -507,7 +507,8 @@ struct XilinxDspPass : public Pass {
 		log("\n");
 		log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n");
 		log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
-		log("used to override the existing accumulation result with a new value.\n");
+		log("used to override the current accumulation result with a new value, which will\n");
+        log("be added to the multiplier result to form the next accumulation result.\n");
 		log("\n");
 		log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n");
 		log("connections (optionally, where 'P' is right-shifted by 18-bits and used as an\n");