From: Sebastien Bourdeauducq Date: Sun, 19 Feb 2012 16:57:04 +0000 (+0100) Subject: bus/dfi: fix multiphase naming X-Git-Tag: 24jan2021_ls180~2099^2~1007 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b8cb5b46ce7228eab43141ff8810afab7bd4322;p=litex.git bus/dfi: fix multiphase naming --- diff --git a/migen/bus/dfi.py b/migen/bus/dfi.py index b2137cb3..b6f407d5 100644 --- a/migen/bus/dfi.py +++ b/migen/bus/dfi.py @@ -34,9 +34,9 @@ class Interface: if (m2s and signal[0] == M_TO_S) or (s2m and signal[0] == S_TO_M): if add_suffix: if signal[0] == M_TO_S: - suffix = "_p" + int(n) + suffix = "_p" + str(n) else: - suffix = "_w" + int(n) + suffix = "_w" + str(n) else: suffix = "" r.append(("dfi_" + signal[1] + suffix, getattr(phase, signal[1])))