From: lkcl <lkcl@web>
Date: Fri, 24 Nov 2023 21:40:53 +0000 (+0000)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b959d89c0510ed56a12c676eb10c4027d93820e;p=libreriscv.git

---

diff --git a/meetings/dmitry_2023-11-24.mdwn b/meetings/dmitry_2023-11-24.mdwn
index 97e72d424..5356ef97c 100644
--- a/meetings/dmitry_2023-11-24.mdwn
+++ b/meetings/dmitry_2023-11-24.mdwn
@@ -25,19 +25,20 @@ full feature set of SimpleV. Link to LibreSOC'
 
 ## New Binutils Grant
 
-- [[nlnet_2023_svp64_riscv_binutils]]
+- [[nlnet_2023_simplev_riscv_binutils]]
 
 - Primarily Dmitry doing most of the work.
 
 ## Primary Tasks
 
   1. Finish writing libopid, some of the work started 4 months ago
-(no RfPs will be submitted for that work). Link to
+(no RfPs can be submitted for that work). Link to
 [repo](https://git.libre-soc.org/?p=mdis.git;a=summary)
-  2. Convert existing PowerISA (SFFS) `isndb` instruction database to libopid.
+  2. Convert existing PowerISA (SFFS) `isndb` instruction database to libopid
+   (without losing CSV files which are machine-readable by other projects)
   3. Create RISC-V instruction database using libopid.
   4. Implement SVP64 PowerISA in libopid.
-  5. Implement SV for RISC-V in libopid.
+  5. Implement SimpleV for RISC-V in libopid.
      - SVP32 (16+16) - 16-bit prefix for 16-bit compressed instructions.
      - SVP48 (16+32) - 16-bit prefix for 32-bit instructions.
      - SVP64 (32+32) - 32-bit prefix for 64-bit instructions.