From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 24 Oct 2018 04:39:20 +0000 (+0100)
Subject: make common function for getting bitwidth
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b9f2de77a8d7bfd5c95e39b80f7273855c91696;p=riscv-isa-sim.git

make common function for getting bitwidth
---

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 3947fc6..53abaf4 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -2,12 +2,12 @@
 #include "sv_decode.h"
 #include "processor.h"
 
-static int get_bitwidth(uint8_t elwidth, int xlen)
+int get_bitwidth(uint8_t elwidth, int xlen)
 {
   switch (elwidth) {
-      case 0: return xlen;
-      case 1: return xlen / 2;
-      case 2: return xlen * 2;
+      case 0: return (xlen == 32)? 64 : 32;
+      case 1: return (xlen == 32)? 32 : 64;
+      case 2: return 16;
       default: return 8;
   }
 }
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 6dd6b41..ac2f581 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -102,9 +102,9 @@ sv_reg_t (sv_proc_t::READ_REG)(uint64_t i)
 
 sv_reg_t sv_proc_t::get_intreg(reg_t reg)
 {
-    uint8_t elwidth = _insn->reg_elwidth(reg, true);
+    //uint8_t elwidth = _insn->reg_elwidth(reg, true);
     uint64_t data = _insn->p->get_state()->XPR[reg];
-    return sv_reg_t(data, xlen, elwidth);
+    return sv_reg_t(data, xlen, _insn->src_bitwidth);
 }
 
 #define GET_REG(name) \
@@ -268,7 +268,7 @@ sv_reg_t::operator sv_reg_t ()
 
 sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs)
 {
-    uint8_t elwidth = lhs.get_width(rhs);
+    uint8_t bitwidth = _insn->src_bitwidth;
     return lhs + rhs;
 }
 
diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index 07d4111..08fa686 100644
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -6,6 +6,9 @@
 #define sext_bwid(x,wid) (((sreg_t)(x) << (64-wid)) >> (64-wid))
 #define zext_bwid(x,wid) (((reg_t)(x) << (64-wid)) >> (64-wid))
 
+extern int get_bitwidth(uint8_t elwidth, int xlen);
+
+
 class sv_sreg_t;
 
 class sv_regbase_t {
@@ -21,37 +24,10 @@ public:
     uint8_t elwidth;
 public:
   int get_xlen() const { return xlen; }
-  uint8_t get_width() const { return elwidth; }
-  uint8_t get_width(sv_regbase_t const&r) const
-  {
-    // bitfield 0b00=default, 0b01=default/2, 0b10=default*2, 0b11=8-bit
-    uint8_t tb[16] = { 0x0, // default-default: default
-                       0x0, // default-default/2: default
-                       0x2, // default-default*2: default*2
-                       0x0, // default-8: default
-                       0x0, // default/2-default: default
-                       0x1, // default/2-default/2: default/2
-                       0x2, // default/2-default*2: default*2
-                       0x1, // default/2-8: default*2
-                       0x2, // default*2-default: default*2
-                       0x2, // default*2-default/2: default*2
-                       0x2, // default*2-default*2: default*2
-                       0x2, // default*2-8: default*2
-                       0x0, // 8-default: default
-                       0x1, // 8-default/2: default/2
-                       0x2, // 8-default*2: default*2
-                       0x3  // 8-8: 8
-                    };
-    return tb[elwidth|(r.elwidth<<2)];
-  }
+  uint8_t get_elwidth() const { return elwidth; }
   int get_bitwidth() const
   {
-    switch (elwidth) {
-        case 0: return xlen;
-        case 1: return xlen / 2;
-        case 2: return xlen * 2;
-        default: return 8;
-    }
+    return ::get_bitwidth(elwidth, xlen);
   }
   int get_bitwidth(sv_regbase_t const&r) const
   {
@@ -88,7 +64,7 @@ public:
 public:
 
   operator int64_t() const& { return reg; }
-  operator sv_reg_t() const& { return sv_reg_t((uint64_t)reg, get_width()); }
+  operator sv_reg_t() const& { return sv_reg_t((uint64_t)reg, get_elwidth()); }
 };
 
 inline sv_reg_t::operator sv_sreg_t() const &