From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 26 Aug 2019 20:56:31 +0000 (-0700)
Subject: Merge branch 'master' into eddie/xilinx_srl
X-Git-Tag: working-ls180~1085^2~22
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ba09c4ab79e066bcd73024bcd97f99321373b58;p=yosys.git

Merge branch 'master' into eddie/xilinx_srl
---

1ba09c4ab79e066bcd73024bcd97f99321373b58
diff --cc CHANGELOG
index 5848ae705,113aae820..df537b30e
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -28,19 -31,15 +31,17 @@@ Yosys 0.9 .. Yosys 0.9-de
      - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
      - Removed "ice40_unlut"
      - Improvements in pmgen: slices, choices, define, generate
 +    - Added "xilinx_srl" for Xilinx shift register extraction
 +    - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
  
- Yosys 0.8 .. Yosys 0.8-dev
- --------------------------
+ Yosys 0.8 .. Yosys 0.9
+ ----------------------
  
   * Various
-     - Added $changed support to read_verilog
+     - Many bugfixes and small improvements
+     - Added support for SystemVerilog interfaces and modports
      - Added "write_edif -attrprop"
-     - Added "ice40_unlut" pass
      - Added "opt_lut" pass
-     - Added "synth_ice40 -relut"
-     - Added "synth_ice40 -noabc"
      - Added "gate2lut.v" techmap rule
      - Added "rename -src"
      - Added "equiv_opt" pass
diff --cc techlibs/xilinx/synth_xilinx.cc
index 5e9cd8a0e,87f4af8f7..5f6ad7522
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -377,16 -389,10 +383,18 @@@ struct SynthXilinxPass : public ScriptP
  			run("clean");
  		}
  
 +		if (check_label("map_ffs")) {
 +				if (abc9 || help_mode) {
 +						run("techmap -map +/xilinx/ff_map.v", "('-abc9' only)");
 +						run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 +										"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "('-abc9' only)");
 +				}
 +		}
 +
  		if (check_label("map_luts")) {
  			run("opt_expr -mux_undef");
+ 			if (flatten_before_abc)
+ 				run("flatten");
  			if (help_mode)
  				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
  			else if (abc9) {