From: lkcl <lkcl@web>
Date: Sat, 28 May 2022 12:46:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2051
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ba7e524571d38e0de30a9eb29b02c4621b1e288;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index e5d39eb22..fb2e099b9 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -10,7 +10,7 @@ SV is designed as a Vector ISA for Hybrid 3D CPU GPU VPU workloads.
 As such it brings features normally only found in Cray Supercomputers
 (Cray-1, NEC SX-Aurora)
 and in GPUs, but keeps strictly to a *Simple* principle of leveraging
-a *Scalar* ISA, exclisively using "Prefixing". **Not one single actual
+a *Scalar* ISA, exclusively using "Prefixing". **Not one single actual
 explicit Vector opcode exists in SV, at all**.
 
 Fundamental design principles: