From: lkcl <lkcl@web>
Date: Wed, 16 Dec 2020 08:36:46 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1295
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1bb976dd832cb0398167bc6d5d516b09e11a3f16;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index cad0d2b65..78fd25ce5 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -65,8 +65,12 @@ note in [[discussion]]: TODO, evaluate if 2nd SUBVL should be added.
 
 ## R\*_EXTRA Encoding
 
+(**TODO: 2-bit version of the table, just like in the original SVPrefix.  This is important, to save bits on 4-operand instructions such as fmadd**)
+
 In the following table, `<N>` denotes the value of the corresponding register field in the SVP64 suffix word. 
 
+(**Jacob: these tables are not in the slightest bit understandable due to the use of register names that are impossible to interpret clearly**)
+
 | R\*_EXTRA | Vector/Scalar<br/>Mode | CR Register   | Int/FP<br/>Register |
 |-----------|------------------------|---------------|---------------------|
 | 000       | Scalar                 | `SVCR<N>_000` | `SV[F]R<N>_00`      |
@@ -250,6 +254,8 @@ pseudocode:
 
 Standard PowerISA Integer registers are aliased to some of the SV integer registers:
 
+(**Jacob these names are impossible to interpret due to them not being sequential numbering and there being no compact algorithm given that shows how they're created.  the original SVPrefix was dead easy to understand**)
+
 | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register |
 |----------------------|-------------------------|----------------------|-------------------------|----------------------|-------------------------|----------------------|-------------------------|
 | R0                   | SVR0_00                 | R8                   | SVR8_00                 | R16                  | SVR16_00                | R24                  | SVR24_00                |
@@ -289,6 +295,8 @@ Standard PowerISA Integer registers are aliased to some of the SV integer regist
 
 Standard PowerISA floating-point and VSX registers are aliased to some of the SV floating-point registers:
 
+(**Jacob these names are impossible to interpret due to them not being sequential numbering and there being no compact algorithm given that shows how they're created.  the original SVPrefix was dead easy to understand**)
+
 | FP<br/>Register | VSX Register          | SV FP<br/>Register | FP<br/>Register | VSX Register          | SV FP<br/>Register |
 |-----------------|-----------------------|--------------------|-----------------|-----------------------|--------------------|
 | FPR\[0\]        | VSR\[0\]\.dword\[0\]  | SVFR0\_00          | FPR\[16\]       | VSR\[16\]\.dword\[0\] | SVFR16\_00         |
@@ -380,6 +388,8 @@ There are 3 new SPRs for holding CRs: CR_EXT1, CR_EXT2, and CR_EXT3.
 
 The 64 SV CRs are arranged similarly to the way the 128 integer registers are arranged:
 
+(**Jacob these names are impossible to interpret due to them not being sequential numbering and there being no compact algorithm given that shows how they're created.  the original SVPrefix was dead easy to understand**)
+
 | CR<br/>Register | SPR<br/>Field  | SV CR<br/>Register | CR<br/>Register | SPR<br/>Field  | SV CR<br/>Register |
 |-----------------|----------------|--------------------|-----------------|----------------|--------------------|
 | CR[0]           | CR[32:35]      | SVCR0_000          | CR[4]           | CR[48:51]      | SVCR4_000          |