From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Mon, 29 Aug 2011 10:10:23 +0000 (-0500)
Subject: Ruby: Remove some unused code
X-Git-Tag: stable_2012_02_02~105
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1bbca50491202c6527743fcca9030d55b4ddc06b;p=gem5.git

Ruby: Remove some unused code
---

diff --git a/src/mem/ruby/buffers/MessageBuffer.cc b/src/mem/ruby/buffers/MessageBuffer.cc
index 9bb166e05..cab98cee9 100644
--- a/src/mem/ruby/buffers/MessageBuffer.cc
+++ b/src/mem/ruby/buffers/MessageBuffer.cc
@@ -161,16 +161,12 @@ MessageBuffer::enqueue(MsgPtr message, Time delta)
     }
     m_msgs_this_cycle++;
 
-    //  assert(m_max_size == -1 || m_size <= m_max_size + 1);
-    // the plus one is a kluge because of a SLICC issue
-
     if (!m_ordering_set) {
         panic("Ordering property of %s has not been set", m_name);
     }
 
     // Calculate the arrival time of the message, that is, the first
     // cycle the message can be dequeued.
-    //printf ("delta %i \n", delta);
     assert(delta>0);
     Time current_time = g_eventQueue_ptr->getTime();
     Time arrival_time = 0;
diff --git a/src/mem/ruby/common/TypeDefines.hh b/src/mem/ruby/common/TypeDefines.hh
index 78d9d618b..2e8d308e2 100644
--- a/src/mem/ruby/common/TypeDefines.hh
+++ b/src/mem/ruby/common/TypeDefines.hh
@@ -40,12 +40,8 @@ typedef int int32;
 typedef long long int64;
 
 typedef long long integer_t;
-typedef unsigned long long uinteger_t;
 
 typedef int64 Time;
 typedef uint64 physical_address_t;
-typedef uint64 la_t;
-typedef uint64 pa_t;
-typedef integer_t simtime_t;
 
 #endif
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc
index a1066f2ad..645d1b4f1 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -30,7 +30,6 @@
 #include <numeric>
 
 #include "base/stl_helpers.hh"
-#include "mem/protocol/MachineType.hh"
 #include "mem/protocol/TopologyType.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
 #include "mem/ruby/common/NetDest.hh"
@@ -46,18 +45,6 @@
 using namespace std;
 using m5::stl_helpers::deletePointers;
 
-#if 0
-// ***BIG HACK*** - This is actually code that _should_ be in Network.cc
-
-// Note: Moved to Princeton Network
-// calls new to abstract away from the network
-Network*
-Network::createNetwork(int nodes)
-{
-    return new SimpleNetwork(nodes);
-}
-#endif
-
 SimpleNetwork::SimpleNetwork(const Params *p)
     : Network(p)
 {
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index c355ae2e3..f0acba9cb 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -36,7 +36,6 @@
 #include "base/hashmap.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/protocol/GenericRequestType.hh"
-#include "mem/protocol/MachineType.hh"
 #include "mem/protocol/RubyRequest.hh"
 #include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/Address.hh"
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index ceed068e8..711ef12ed 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -504,11 +504,6 @@ Sequencer::hitCallback(SequencerRequest* srequest,
                  success ? "Done" : "SC_Failed", "", "",
                  ruby_request.m_PhysicalAddress, miss_latency);
     }
-#if 0
-    if (request.getPrefetch() == PrefetchBit_Yes) {
-        return; // Ignore the prefetch
-    }
-#endif
 
     // update the data
     if (ruby_request.data != NULL) {
@@ -702,19 +697,6 @@ Sequencer::issueRequest(const RubyRequest& request)
     m_mandatory_q_ptr->enqueue(msg, latency);
 }
 
-#if 0
-bool
-Sequencer::tryCacheAccess(const Address& addr, RubyRequestType type,
-                          RubyAccessMode access_mode,
-                          int size, DataBlock*& data_ptr)
-{
-    CacheMemory *cache =
-        (type == RubyRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
-
-    return cache->tryCacheAccess(line_address(addr), type, data_ptr);
-}
-#endif
-
 template <class KEY, class VALUE>
 std::ostream &
 operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 885910251..0589d8bbc 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -112,9 +112,6 @@ class Sequencer : public RubyPort, public Consumer
     void removeRequest(SequencerRequest* request);
 
   private:
-    bool tryCacheAccess(const Address& addr, RubyRequestType type,
-                        const Address& pc, RubyAccessMode access_mode,
-                        int size, DataBlock*& data_ptr);
     void issueRequest(const RubyRequest& request);
 
     void hitCallback(SequencerRequest* request,