From: lkcl Date: Fri, 19 Feb 2021 15:11:30 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~151 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1bcfca695ed465a529d279a55f38e992a370c946;p=libreriscv.git --- diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn index cd1b93c3f..9acd84284 100644 --- a/shakti/m_class.mdwn +++ b/shakti/m_class.mdwn @@ -14,7 +14,7 @@ yields. ## Rough specification. -Quad-core 28nm RISC-V 64-bit (RISCV64GC core with Vector SIMD Media / 3D +Quad-core 28nm OpenPOWER 64-bit (OpenPOWER v3.0B core with Simple-V Vector Media / 3D extensions), 300-pin 15x15mm BGA 0.8mm pitch, 32-bit DDR3-4/LPDDR3/4 memory interface and libre / open interfaces and accelerated hardware functions suitable for the higher-end, low-power, embedded, industrial @@ -182,7 +182,7 @@ image acceleration, scalable fonts, and Z-buffering and much more. * MIAOW: ATI-compatible shader engine * ORSOC GPU contains some primitives that can be used -* SIMD RISC-V extensions can obviate the need for a "full" separate GPU +* Simple-V Vector extensions can obviate the need for a "full" separate GPU * Nyuzi (OpenMP, based on Intel Larabee Compute Engine) * Rasteriser * OpenShader