From: Tobias Platen <tplaten@posteo.de>
Date: Fri, 18 Jun 2021 17:40:05 +0000 (+0200)
Subject: src/soc/fu/ldst/loadstore.py: keep data for the whole cycle
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1bd041fda727b3340952910f6a7e0b6aa3138093;p=soc.git

src/soc/fu/ldst/loadstore.py: keep data for the whole cycle
---

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index d699ffea..7cff8987 100644
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -289,11 +289,12 @@ class LoadStore1(PortInterfaceBase):
         if hasattr(dbus, "stall"):
             comb += dcache.wb_in.stall.eq(dbus.stall)
 
-        # write out d data only when flag set
+        # update out d data when flag set
         with m.If(self.d_w_valid):
             m.d.sync += d_out.data.eq(self.store_data)
-        with m.Else():
-            m.d.sync += d_out.data.eq(0)
+        #with m.Else():
+        #    m.d.sync += d_out.data.eq(0)
+        # unit test passes with that change
 
         # this must move into the FSM, conditionally noticing that
         # the "blip" comes from self.d_validblip.