From: Luke Kenneth Casson Leighton Date: Wed, 28 Apr 2021 17:22:57 +0000 (+0000) Subject: name everything back to spblock_512w64b8w now that missing blackbox X-Git-Tag: LS180_RC3~75 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1bd1586649497717851400bbe77d8e8a05bd98a4;p=soclayout.git name everything back to spblock_512w64b8w now that missing blackbox cell issue has been found --- diff --git a/experiments9/coriolis2/settings.py b/experiments9/coriolis2/settings.py index 5c1ea66..b97952c 100644 --- a/experiments9/coriolis2/settings.py +++ b/experiments9/coriolis2/settings.py @@ -1,9 +1,12 @@ # -*- Mode:Python -*- import Cfg +from Hurricane import DataBase, Cell, Instance, Net +from CRL import AllianceFramework, RoutingLayerGauge import CRL import Viewer from helpers.overlay import CfgCache +from helpers import overlay, l, u, n import symbolic.cmos45 # do not remove import os @@ -12,6 +15,46 @@ if os.environ.has_key('CELLS_TOP'): else: cellsTop = '../../../alliance-check-toolkit/cells' +db = DataBase.getDB() +af = AllianceFramework.get() + + +def createSramBlackbox (): + global db, af + print( ' o Creating SRAM blackboxes for "ls180" design.' ) + rootlib = db.getRootLibrary() + lib = rootlib.getLibrary( 'LibreSOCMem' ) + sramName = 'spblock_512w64b8w' + sram = lib.getCell( sramName ) + if not sram: + raise ErrorMessage( 1, 'settings.createSramBlocks(): ' + 'SRAM Cell "{}" not found.' \ + .format(sramName) ) + sram.setAbstractedSupply( True ) + blackboxeNames = [ 'spblock_512w64b8w' + ] + for blackboxName in blackboxeNames: + cell = Cell.create( lib, blackboxName ) + instance = Instance.create( cell, 'real_sram', sram ) + state = af.getCatalog().getState( blackboxName, True ) + state.setCell( cell ) + state.setLogical( True ) + state.setInMemory( True ) + print( ' - {}.'.format(cell) ) + for masterNet in sram.getNets(): + if not masterNet.isExternal(): + continue + net = Net.create( cell, masterNet.getName() ) + net.setDirection( masterNet.getDirection() ) + net.setType( masterNet.getType() ) + net.setExternal( True ) + net.setGlobal( masterNet.isGlobal() ) + if masterNet.isSupply(): + continue + plug = instance.getPlug( masterNet ) + plug.setNet( net ) + + with CfgCache('', priority=Cfg.Parameter.Priority.UserFile) as cfg: cfg.misc.catchCore = False cfg.misc.info = False @@ -75,5 +118,12 @@ with CfgCache('', priority=Cfg.Parameter.Priority.UserFile) as cfg: Viewer.Graphics.setStyle('Alliance.Classic [black]') +# XXX cannot run this in non-NDA'd mode because there is no +# equivalent to NDA.node180.tsmc_c018.LibreSOCMem (or PLL) +# TODO: create a fake one +#with overlay.UpdateSession(): +# createSramBlackbox() + print( ' o Successfully run "<>/coriolis2/settings.py".' ) print( ' - CELLS_TOP = "{}"'.format(cellsTop) ) + diff --git a/experiments9/freepdk_c4m45/coriolis2/settings.py b/experiments9/freepdk_c4m45/coriolis2/settings.py index 5a7e6c3..5988d94 100644 --- a/experiments9/freepdk_c4m45/coriolis2/settings.py +++ b/experiments9/freepdk_c4m45/coriolis2/settings.py @@ -47,10 +47,7 @@ def createSramBlackbox (): 'SRAM Cell "{}" not found.' \ .format(sramName) ) sram.setAbstractedSupply( True ) - blackboxeNames = [ 'spblock512w64b8w_0' - , 'spblock512w64b8w_1' - , 'spblock512w64b8w_2' - , 'spblock512w64b8w_3' + blackboxeNames = [ 'spblock_512w64b8w' ] for blackboxName in blackboxeNames: cell = Cell.create( lib, blackboxName ) @@ -94,5 +91,8 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: env = af.getEnvironment() env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' ) +# XXX cannot run this in non-NDA'd mode because there is no +# NDA.node45.freepdk45_c4m.LibreSOCMem (or PLL) +# TODO: create a fake one with overlay.UpdateSession(): createSramBlackbox() diff --git a/experiments9/non_generated/full_core_4_4ksram_libresoc.v b/experiments9/non_generated/full_core_4_4ksram_libresoc.v index 6f3af85..d504dac 100644 --- a/experiments9/non_generated/full_core_4_4ksram_libresoc.v +++ b/experiments9/non_generated/full_core_4_4ksram_libresoc.v @@ -193401,7 +193401,7 @@ module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ac assign \$1 = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_0_wb__stb; always @(posedge clk) sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ; - spblock_512w64b8w spblock512w64b8w_0 ( + spblock_512w64b8w spblock_512w64b8w ( .a(a), .clk(clk), .d(d), @@ -193545,7 +193545,7 @@ module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ac assign \$1 = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_1_wb__stb; always @(posedge clk) sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ; - spblock_512w64b8w spblock512w64b8w_1 ( + spblock_512w64b8w spblock_512w64b8w ( .a(a), .clk(clk), .d(d), @@ -193689,7 +193689,7 @@ module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ac assign \$1 = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_2_wb__stb; always @(posedge clk) sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ; - spblock_512w64b8w spblock512w64b8w_2 ( + spblock_512w64b8w spblock_512w64b8w ( .a(a), .clk(clk), .d(d), @@ -193833,7 +193833,7 @@ module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ac assign \$1 = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_3_wb__stb; always @(posedge clk) sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ; - spblock_512w64b8w spblock512w64b8w_3 ( + spblock_512w64b8w spblock_512w64b8w ( .a(a), .clk(clk), .d(d), diff --git a/experiments9/non_generated/spblock512w64b8w.v b/experiments9/non_generated/spblock512w64b8w.v deleted file mode 100644 index 4555b15..0000000 --- a/experiments9/non_generated/spblock512w64b8w.v +++ /dev/null @@ -1,9 +0,0 @@ -<* blackbox = 1 *) -module spblock_512w64b8w(a, d, q, we, clk); - input [8:0] a; - input [63:0] d; - output [63:0] q; - input [7:0] we; - input clk; -endmodule // SPBlock_512W64B8W - diff --git a/experiments9/non_generated/spblock512w64b8w.vbe b/experiments9/non_generated/spblock512w64b8w.vbe deleted file mode 100644 index de2d3df..0000000 --- a/experiments9/non_generated/spblock512w64b8w.vbe +++ /dev/null @@ -1,18 +0,0 @@ --- Phony VHDL interface for SRAM block. - -entity spblock512w64b8w is - port ( clk : in bit - ; we : in bit_vector( 7 downto 0) - ; a : in bit_vector( 8 downto 0) - ; d : in bit_vector(63 downto 0) - ; q : out bit_vector(63 downto 0) - ; vdd : in bit - ; vss : in bit - ); -end spblock512w64b8w; - -architecture behavioral of spblock512w64b8w is - -begin - -end behavioral; diff --git a/experiments9/non_generated/spblock_512w64b8w.v b/experiments9/non_generated/spblock_512w64b8w.v new file mode 100644 index 0000000..4555b15 --- /dev/null +++ b/experiments9/non_generated/spblock_512w64b8w.v @@ -0,0 +1,9 @@ +<* blackbox = 1 *) +module spblock_512w64b8w(a, d, q, we, clk); + input [8:0] a; + input [63:0] d; + output [63:0] q; + input [7:0] we; + input clk; +endmodule // SPBlock_512W64B8W + diff --git a/experiments9/non_generated/spblock_512w64b8w.vbe b/experiments9/non_generated/spblock_512w64b8w.vbe new file mode 100644 index 0000000..999c8da --- /dev/null +++ b/experiments9/non_generated/spblock_512w64b8w.vbe @@ -0,0 +1,18 @@ +-- Phony VHDL interface for SRAM block. + +entity spblock_512w64b8w is + port ( clk : in bit + ; we : in bit_vector( 7 downto 0) + ; a : in bit_vector( 8 downto 0) + ; d : in bit_vector(63 downto 0) + ; q : out bit_vector(63 downto 0) + ; vdd : in bit + ; vss : in bit + ); +end spblock_512w64b8w; + +architecture behavioral of spblock_512w64b8w is + +begin + +end behavioral; diff --git a/experiments9/tsmc_c018/coriolis2/settings.py b/experiments9/tsmc_c018/coriolis2/settings.py index cd26638..80211c3 100644 --- a/experiments9/tsmc_c018/coriolis2/settings.py +++ b/experiments9/tsmc_c018/coriolis2/settings.py @@ -46,10 +46,7 @@ def createSramBlackbox (): raise ErrorMessage( 1, 'settings.createSramBlocks(): SRAM Cell "{}" not found.' \ .format(sramName) ) sram.setAbstractedSupply( True ) - blackboxeNames = [ 'spblock512w64b8w_0' - , 'spblock512w64b8w_1' - , 'spblock512w64b8w_2' - , 'spblock512w64b8w_3' + blackboxeNames = [ 'spblock_512w64b8w' # go back to only one blackbox ] for blackboxName in blackboxeNames: cell = Cell.create( lib, blackboxName )