From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 2 Jan 2015 16:11:54 +0000 (+0100)
Subject: Define YOSYS and SYNTHESIS in preproc
X-Git-Tag: yosys-0.5~147
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1bd67d792eefeb7e72bf74f80776b0d5e41d771a;p=yosys.git

Define YOSYS and SYNTHESIS in preproc
---

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index b4e77c31b..4e5d16599 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -221,7 +221,8 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
 	input_buffer_charp = 0;
 
 	input_file(f, filename);
-	defines_map["__YOSYS__"] = "1";
+	defines_map["YOSYS"] = "1";
+	defines_map["SYNTHESIS"] = "1";
 
 	while (!input_buffer.empty())
 	{