From: Gabe Black <gabeblack@google.com>
Date: Tue, 26 Nov 2019 01:12:12 +0000 (-0800)
Subject: arm: Call pseudoInst directly from the mmapped IPR handlers.
X-Git-Tag: v19.0.0.0~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1bd9687799d931094781fd3aff304664f2203787;p=gem5.git

arm: Call pseudoInst directly from the mmapped IPR handlers.

The amount of plumbing necessary for the generic IPR mechanism out
weighs its value, considering it's only used for the m5ops.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I0efcf43904d5f779bef5ad127dd8d39fff41ac39
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23185
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/mmapped_ipr.hh b/src/arch/arm/mmapped_ipr.hh
index d515b8371..1cccdbd79 100644
--- a/src/arch/arm/mmapped_ipr.hh
+++ b/src/arch/arm/mmapped_ipr.hh
@@ -39,14 +39,44 @@
  * ISA-specific helper functions for memory mapped IPR accesses.
  */
 
-#include "arch/generic/mmapped_ipr.hh"
+#include "base/types.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "sim/pseudo_inst.hh"
+#include "sim/system.hh"
 
 class ThreadContext;
 
 namespace ArmISA
 {
-    using GenericISA::handleIprRead;
-    using GenericISA::handleIprWrite;
+
+inline Cycles
+handleIprRead(ThreadContext *tc, Packet *pkt)
+{
+    Addr addr = pkt->getAddr();
+    auto m5opRange = tc->getSystemPtr()->m5opRange();
+    if (m5opRange.contains(addr)) {
+        uint8_t func;
+        PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
+        uint64_t ret = PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
+        pkt->setLE(ret);
+    }
+    return Cycles(1);
+}
+
+inline Cycles
+handleIprWrite(ThreadContext *tc, Packet *pkt)
+{
+    Addr addr = pkt->getAddr();
+    auto m5opRange = tc->getSystemPtr()->m5opRange();
+    if (m5opRange.contains(addr)) {
+        uint8_t func;
+        PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
+        PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
+    }
+    return Cycles(1);
+}
+
 } // namespace ArmISA
 
 #endif
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5ecd7a45c..5358159fb 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -138,12 +138,8 @@ TLB::finalizePhysical(const RequestPtr &req,
 {
     const Addr paddr = req->getPaddr();
 
-    if (m5opRange.contains(paddr)) {
-        req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
-        req->setPaddr(GenericISA::iprAddressPseudoInst(
-                          (paddr >> 8) & 0xFF,
-                          paddr & 0xFF));
-    }
+    if (m5opRange.contains(paddr))
+        req->setFlags(Request::MMAPPED_IPR);
 
     return NoFault;
 }