From: Matthew Malcomson <matthew.malcomson@arm.com>
Date: Thu, 9 May 2019 09:29:23 +0000 (+0100)
Subject: [binutils][aarch64] New sve_shift_tsz_bhsd iclass.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1be5f94f9c85821287b9ae423f738a8bab499526;p=binutils-gdb.git

[binutils][aarch64] New sve_shift_tsz_bhsd iclass.

This new iclass encodes the variant by which is the most significant bit
used of bits 23-22:20-19, where those bits are usually part of a
given constant operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
	iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_shift_tsz_bhsd iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_shift_tsz_bhsd iclass decode.
---

diff --git a/include/ChangeLog b/include/ChangeLog
index 3b389d54485..65cdf2b6d2b 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
+	iclass.
+
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
 	* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index bd6b845a134..d1d366b439c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -599,6 +599,7 @@ enum aarch64_insn_class
   sve_size_sd2,
   sve_size_013,
   sve_shift_tsz_hsd,
+  sve_shift_tsz_bhsd,
   testbranch,
   cryptosm3,
   cryptosm4,
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2ab1845dc55..8e8614206cb 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+	sve_shift_tsz_bhsd iclass encode.
+	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+	sve_shift_tsz_bhsd iclass decode.
+
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
 	* aarch64-asm-2.c: Regenerated.
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 6be17f9246e..ad50598fd0e 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1626,6 +1626,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
     case sve_shift_pred:
     case sve_shift_unpred:
     case sve_shift_tsz_hsd:
+    case sve_shift_tsz_bhsd:
       /* For indices and shift amounts, the variant is encoded as
 	 part of the immediate.  */
       break;
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 5571ab6c98f..b42e4d594c6 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2832,6 +2832,17 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
 	variant = i;
       break;
 
+    case sve_shift_tsz_bhsd:
+      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
+      if (i == 0)
+	return FALSE;
+      while (i != 1)
+	{
+	  i >>= 1;
+	  variant += 1;
+	}
+      break;
+
     case sve_shift_tsz_hsd:
       i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
       if (i == 0)