From: Luke Kenneth Casson Leighton Date: Tue, 24 Apr 2018 07:51:53 +0000 (+0100) Subject: add clarification X-Git-Tag: convert-csv-opcode-to-binary~5593 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1bebaf7c77a585e0cf35235616c70b2f8bbeb607;p=libreriscv.git add clarification --- diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 226c0b1a8..92ac117ed 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -52,10 +52,13 @@ details outlined in the Appendix), the key points being: * Vectorisation typically includes much more comprehensive memory load and store schemes (unit stride, constant-stride and indexed), which in turn have ramifications: virtual memory misses (TLB cache misses) - and even multiple page-faults... all caused by a *single instruction*. + and even multiple page-faults... all caused by a *single instruction*, + yet with a clear benefit that the regularisation of LOAD/STOREs can + be optimised for minimal impact on caches and maximised throughput. * By contrast, SIMD can use "standard" memory load/stores (32-bit aligned to pages), and these load/stores have absolutely nothing to do with the - SIMD / ALU engine, no matter how wide the operand. + SIMD / ALU engine, no matter how wide the operand. Simplicity but with + more impact on instruction and data caches. Overall it makes a huge amount of sense to have a means and method of introducing instruction parallelism in a flexible way that provides