From: Claire Wolf Date: Fri, 27 Mar 2020 16:28:26 +0000 (+0100) Subject: Merge pull request #1607 from whitequark/simplify-simplify-meminit X-Git-Tag: working-ls180~726 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1bf2bdf05bd78a08f932780d99144b2d56e2943f;p=yosys.git Merge pull request #1607 from whitequark/simplify-simplify-meminit ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT --- 1bf2bdf05bd78a08f932780d99144b2d56e2943f