From: Florent Kermarrec Date: Sat, 21 Mar 2015 17:07:10 +0000 (+0100) Subject: targets/kc705: rename sdram_module to sdram_modules to reflect that we have 8 modules... X-Git-Tag: 24jan2021_ls180~2463 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c0e3061761d95dc7f03820c592d326b3364d47c;p=litex.git targets/kc705: rename sdram_module to sdram_modules to reflect that we have 8 modules sharing the same characteristics --- diff --git a/targets/kc705.py b/targets/kc705.py index 81eec083..db6d4834 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -84,14 +84,14 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = _CRG(platform) if not self.with_main_ram: - sdram_module = MT8JTF12864(self.clk_freq) + sdram_modules = MT8JTF12864(self.clk_freq) sdram_controller_settings = sdram.ControllerSettings( req_queue_size=8, read_time=32, write_time=16 ) self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3") - self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, + self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings, sdram_controller_settings) spiflash_pads = platform.request("spiflash")