From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 Date: Tue, 9 Mar 2021 18:55:39 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~65 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c16445a180f8053684f1c9518fc26983c052816;p=libreriscv.git --- diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn index 7f9875991..b3ac31c1e 100644 --- a/HDL_workflow/ECP5_FPGA.mdwn +++ b/HDL_workflow/ECP5_FPGA.mdwn @@ -102,6 +102,12 @@ Finally, we will connect the jumper cables of the same colour from STLINKv2 and | Attach the ends of the **WHITE** jumper cables | | Attach the ends of the **YELLOW** jumper cables | +Connect the ***ONLY*** USB-to-MicroUSB cable to the STLINKv2 ***ONLY***. This should be the ***ONLY*** USB cable connected to the setup of the STLINKv2 and the FPGA board. The ***ONLY*** things connected to the FPGA board are the coloured jumper cables from the above steps. + +If there are multiple USB cables connected the FPGA ***WILL*** be ***DAMAGED***. + +Finally, plug in the USB end of the USB-to-MicroUSB cable that is plugged into the STLINKv2 into your computer. Begin testing the SOC on the FPGA (instructions to follow). + ## Connecting the dots: Accurate render of board for reference