From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Oct 2018 09:24:25 +0000 (+0100)
Subject: create ldsp immediate offset overrides
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c35bd706f38198f65b0001552cd6a37c9bb066c;p=riscv-isa-sim.git

create ldsp immediate offset overrides

this allows C.LWSP/C.LDSP to do predicated load/stores from contiguous
blocks of memory
---

diff --git a/id_regs.py b/id_regs.py
index 782cbcb..d6259cd 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -129,6 +129,12 @@ def find_registers(fname, insn, twin_predication, immed_offset):
     if immed_offset: # C.LWSP
         predargs.append('&src_pred')
         fsrc = insn in ['c_flwsp', 'c_fldsp']
+        c_sp_width = {'c_lwsp': 4, 'c_ldsp': 8, 'c_lqsp': 16,
+                      'c_flwsp': 4, 'c_fldsp': 8,
+                      'c_swsp': 4, 'c_sdsp': 8, 'c_sqsp': 16,
+                      'c_fswsp': 4, 'c_fsdsp': 8}
+        iwidth = c_sp_width[insn]
+        res.append('#define IMMEDWIDTH %d' % (iwidth))
         res.append('#define SRC_PREDINT %d' % (0 if fsrc else 1))
 
     if twin_predication:
diff --git a/riscv/sv.cc b/riscv/sv.cc
index a6bf42a..8088ef4 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -92,7 +92,7 @@ uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int voffs)
   // we return the re-mapped register...
   if (!r->isvec) // scalar
   {
-    return reg; 
+    return reg;
   }
   vloop_continue = true;
 
@@ -167,3 +167,25 @@ bool sv_insn_t::stop_vloop(void)
 }
 
 
+/* c_lwsp's immediate offset is turned into a Vector "unit stride" if
+ * x2 (sp by convention) is marked as vectorised.
+ *
+ */
+uint64_t sv_insn_t::_rvc_spoffs_imm(uint64_t elwidth, uint64_t offs)
+{
+  sv_reg_entry *r = get_regentry(X_SP, 1);
+  if (!r->active)
+  {
+    return offs;
+  }
+  vloop_continue = true;
+  reg_t reg = r->regidx;
+  if (!r->isvec)
+  {
+    return offs;
+  }
+  offs += (*offs_imm) * elwidth;
+
+  return offs;
+}
+
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 8065013..d85f047 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -26,7 +26,11 @@ public:
             int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_imm) :
             insn_t(bits), p(pr), vloop_continue(false), fimap(f),
             offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
+            offs_imm(o_imm),
             prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3) {}
+  uint64_t _rvc_spoffs_imm(uint64_t elwidth, uint64_t baseoffs);
+  uint64_t rvc_ldsp_imm() { return _rvc_spoffs_imm(4, insn_t::rvc_ldsp_imm()); }
+  uint64_t rvc_lwsp_imm() { return _rvc_spoffs_imm(8, insn_t::rvc_lwsp_imm()); }
   uint64_t rd () { return predicated(_rd (), *offs_rd, prd); }
   uint64_t rs1() { return predicated(_rs1(), *offs_rs1, prs1); }
   uint64_t rs2() { return predicated(_rs2(), *offs_rs2, prs2); }
@@ -65,6 +69,7 @@ private:
   int *offs_rs1;
   int *offs_rs2;
   int *offs_rs3;
+  int *offs_imm;
   uint64_t &prd;
   uint64_t &prs1;
   uint64_t &prs2;