From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 14 Aug 2014 14:33:59 +0000 (+0200)
Subject: k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate)
X-Git-Tag: 24jan2021_ls180~2661
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c381acc6f97b3e0ae43d42ba77f6b4cd685a548;p=litex.git

k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate)
---

diff --git a/misoclib/sdramphy/k7ddrphy.py b/misoclib/sdramphy/k7ddrphy.py
index 83171224..5d70adfd 100644
--- a/misoclib/sdramphy/k7ddrphy.py
+++ b/misoclib/sdramphy/k7ddrphy.py
@@ -22,7 +22,7 @@ class K7DDRPHY(Module):
 			wrcmdphase=0,
 			cl=8,
 			cwl=6,
-			read_latency=8,
+			read_latency=6,
 			write_latency=2
 		)
 
@@ -211,12 +211,12 @@ class K7DDRPHY(Module):
 				)
 			]
 
-		# total read latency = 8:
+		# total read latency = 6:
 		#  2 cycles through OSERDESE2
-		#  4 cycles CAS
+		#  2 cycles CAS
 		#  2 cycles through ISERDESE2
 		rddata_en = self.dfi.phases[self.phy_settings.rdphase].rddata_en
-		for i in range(7):
+		for i in range(5):
 			n_rddata_en = Signal()
 			self.sync += n_rddata_en.eq(rddata_en)
 			rddata_en = n_rddata_en