From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Mar 2021 17:57:06 +0000 (+0100)
Subject: must not add bus width parameter
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c39d100a02dce4c60a92d29a8c47fe7a6a99b11;p=libresoc-litex.git

must not add bus width parameter
---

diff --git a/ls180soc.py b/ls180soc.py
index 8d2789f..44a4ce8 100755
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -362,7 +362,7 @@ class LibreSoCSim(SoCCore):
             cpu_type                 = "microwatt",
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
-            bus_data_width           = 64,
+            #bus_data_width           = 64, # don't add this! stops conversion
             csr_address_width        = 14, # limit to 0x8000
             cpu_variant              = variant,
             csr_data_width            = 8,