From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 May 2020 12:03:38 +0000 (+0100)
Subject: add 3rd parameter to DummyALU
X-Git-Tag: div_pipeline~769^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c56645c0bbc41691f9f78013b7099278f4cf4da;p=soc.git

add 3rd parameter to DummyALU
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 42f38cb4..438f165a 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -98,8 +98,9 @@ class DummyALU(Elaboratable):
         i = []
         i.append(Signal(width, name="i1"))
         i.append(Signal(width, name="i2"))
+        i.append(Signal(width, name="i3"))
         self.i = Array(i)
-        self.a, self.b = i[0], i[1]
+        self.a, self.b, self.c = i[0], i[1], i[2]
         self.out = Array([Signal(width)])
         self.o = self.out[0]
         self.width = width
@@ -107,6 +108,7 @@ class DummyALU(Elaboratable):
         self.p.data_i.ctx.op = self.op
         self.p.data_i.a = self.a
         self.p.data_i.b = self.b
+        self.p.data_i.c = self.c
         self.n.data_o.o = self.o
 
     def elaborate(self, platform):
@@ -149,6 +151,7 @@ class DummyALU(Elaboratable):
         yield from self.op.ports()
         yield self.a
         yield self.b
+        yield self.c
         yield self.o
 
     def ports(self):