From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 16 Aug 2019 22:56:57 +0000 (-0700)
Subject: Update abc_* attr in ecp5 and ice40
X-Git-Tag: working-ls180~1123^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c57b1e7ea0128aebef8e78bcf4de9aaf9e42c6a;p=yosys.git

Update abc_* attr in ecp5 and ice40
---

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 3d343b315..864a3550f 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
-module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
-	           output S0, S1, COUT);
-
+(* abc_box_id=1, lib_whitebox *)
+module CCU2C(
+	(* abc_carry_in *) input CIN,
+	input  A0, B0, C0, D0, A1, B1, C1, D1,
+	output S0, S1,
+	(* abc_carry_out *) output COUT
+);
 	parameter [15:0] INIT0 = 16'h0000;
 	parameter [15:0] INIT1 = 16'h0000;
 	parameter INJECT1_0 = "YES";
@@ -104,12 +107,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
+//(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-	input [3:0] DI,
-	input [3:0] WAD,
-	input WRE, WCK,
-	input [3:0] RAD,
+	(* abc_scc_break *) input [3:0] DI,
+	(* abc_scc_break *) input [3:0] WAD,
+	(* abc_scc_break *) input       WRE,
+	input        WCK,
+	input  [3:0] RAD,
 	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 2205be27d..5b18fec27 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
-(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
-module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
+(* abc_box_id = 1, lib_whitebox *)
+module \$__ICE40_FULL_ADDER (
+	(* abc_carry_out *) output CO,
+	output O,
+	input A,
+	input B,
+	(* abc_carry_in *) input CI
+);
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),