From: Luke Kenneth Casson Leighton Date: Thu, 1 Apr 2021 12:17:53 +0000 (+0100) Subject: bug in iverilog, segfaults due to empty case statement X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c57d5624977519983f1fcdb96497581c8a2e1f4;p=soc.git bug in iverilog, segfaults due to empty case statement --- diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index e2f66a50..d1a5b2c7 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -680,7 +680,12 @@ class TestIssuerInternal(Elaboratable): comb += self.state_w_pc.wen.eq(1 << StateRegs.PC) comb += self.state_w_pc.data_i.eq(nia) # reset SRCSTEP before returning to Fetch - with m.If(pdecode2.loop_continue): + if self.svp64_en: + with m.If(pdecode2.loop_continue): + comb += new_svstate.srcstep.eq(0) + comb += new_svstate.dststep.eq(0) + comb += update_svstate.eq(1) + else: comb += new_svstate.srcstep.eq(0) comb += new_svstate.dststep.eq(0) comb += update_svstate.eq(1)