From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 4 Dec 2020 04:58:05 +0000 (-0800)
Subject: attempt to fix tables
X-Git-Tag: convert-csv-opcode-to-binary~1514
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c611e3641544fc229e0219a451047d6f0ac5403;p=libreriscv.git

attempt to fix tables
---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 28acbf1bc..4a97a6a7f 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -82,6 +82,7 @@ Standard PowerISA Integer registers are aliased to some of the SV integer regist
 ## Floating-Point Registers
 
 Standard PowerISA floating-point and VSX registers are aliased to some of the SV floating-point registers:
+
 | FP<br/>Register | VSX Register          | SV FP<br/>Register | FP<br/>Register | VSX Register          | SV FP<br/>Register | FP<br/>Register | VSX Register          | SV FP<br/>Register | FP<br/>Register | VSX Register          | SV FP<br/>Register |
 |-----------------|-----------------------|--------------------|-----------------|-----------------------|--------------------|-----------------|-----------------------|--------------------|-----------------|-----------------------|--------------------|
 | FPR\[0\]        | VSR\[0\]\.dword\[0\]  | SVFR0\_00          | FPR\[8\]        | VSR\[8\]\.dword\[0\]  | SVFR8\_00          | FPR\[16\]       | VSR\[16\]\.dword\[0\] | SVFR16\_00         | FPR\[24\]       | VSR\[24\]\.dword\[0\] | SVFR24\_00         |