From: lkcl <lkcl@web>
Date: Thu, 28 Jan 2021 23:25:25 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~263
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c8b2a929335f09c30785a2f545f3bf40205b292;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 58a58f22c..d0b5b87ae 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -80,6 +80,8 @@ This is a peer of MSR but is stored in an SPR.  It should be considered part of
 * TestIssuer: TODO
 * Microwatt: TODO
 
+* <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
+
 ## sv.setvl
 
 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.