From: Diego H <diego@symbioticeda.com>
Date: Fri, 13 Dec 2019 15:33:18 +0000 (-0600)
Subject: Renaming BRAM memory tests for the sake of uniformity
X-Git-Tag: working-ls180~926^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c9634558747bf5b92a309b6af013a54034c35d3;p=yosys.git

Renaming BRAM memory tests for the sake of uniformity
---

diff --git a/tests/arch/common/blockram_params.v b/tests/arch/common/blockram_params.v
new file mode 100644
index 000000000..dbc6ca65c
--- /dev/null
+++ b/tests/arch/common/blockram_params.v
@@ -0,0 +1,45 @@
+`default_nettype none
+module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+   (input  wire                      write_enable, clk,
+    input  wire  [DATA_WIDTH-1:0]    data_in,
+    input  wire  [ADDRESS_WIDTH-1:0] address_in,
+    output wire  [DATA_WIDTH-1:0]    data_out);
+
+   localparam WORD  = (DATA_WIDTH-1);
+   localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+   reg [WORD:0] data_out_r;
+   reg [WORD:0] memory [0:DEPTH];
+
+   always @(posedge clk) begin
+      if (write_enable)
+        memory[address_in] <= data_in;
+      data_out_r <= memory[address_in];
+   end
+
+   assign data_out = data_out_r;
+endmodule // sync_ram_sp
+
+
+`default_nettype none
+module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+   (input  wire                      clk, write_enable,
+    input  wire  [DATA_WIDTH-1:0]    data_in,
+    input  wire  [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
+    output wire  [DATA_WIDTH-1:0]    data_out);
+
+   localparam WORD  = (DATA_WIDTH-1);
+   localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+   reg [WORD:0] data_out_r;
+   reg [WORD:0] memory [0:DEPTH];
+
+   always @(posedge clk) begin
+      if (write_enable)
+        memory[address_in_w] <= data_in;
+      data_out_r <= memory[address_in_r];
+   end
+
+   assign data_out = data_out_r;
+endmodule // sync_ram_sdp
+
diff --git a/tests/arch/common/memory_params.v b/tests/arch/common/memory_params.v
deleted file mode 100644
index dbc6ca65c..000000000
--- a/tests/arch/common/memory_params.v
+++ /dev/null
@@ -1,45 +0,0 @@
-`default_nettype none
-module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
-   (input  wire                      write_enable, clk,
-    input  wire  [DATA_WIDTH-1:0]    data_in,
-    input  wire  [ADDRESS_WIDTH-1:0] address_in,
-    output wire  [DATA_WIDTH-1:0]    data_out);
-
-   localparam WORD  = (DATA_WIDTH-1);
-   localparam DEPTH = (2**ADDRESS_WIDTH-1);
-
-   reg [WORD:0] data_out_r;
-   reg [WORD:0] memory [0:DEPTH];
-
-   always @(posedge clk) begin
-      if (write_enable)
-        memory[address_in] <= data_in;
-      data_out_r <= memory[address_in];
-   end
-
-   assign data_out = data_out_r;
-endmodule // sync_ram_sp
-
-
-`default_nettype none
-module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
-   (input  wire                      clk, write_enable,
-    input  wire  [DATA_WIDTH-1:0]    data_in,
-    input  wire  [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
-    output wire  [DATA_WIDTH-1:0]    data_out);
-
-   localparam WORD  = (DATA_WIDTH-1);
-   localparam DEPTH = (2**ADDRESS_WIDTH-1);
-
-   reg [WORD:0] data_out_r;
-   reg [WORD:0] memory [0:DEPTH];
-
-   always @(posedge clk) begin
-      if (write_enable)
-        memory[address_in_w] <= data_in;
-      data_out_r <= memory[address_in_r];
-   end
-
-   assign data_out = data_out_r;
-endmodule // sync_ram_sdp
-
diff --git a/tests/arch/xilinx/blockram_params.ys b/tests/arch/xilinx/blockram_params.ys
new file mode 100644
index 000000000..27a94834e
--- /dev/null
+++ b/tests/arch/xilinx/blockram_params.ys
@@ -0,0 +1,47 @@
+## TODO: Not running equivalence checking because BRAM models does not exists
+##       currently. Checking instance counts instead.
+# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+# Anything memory bits < 1024 -> LUTRAM
+design -reset
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 0 t:RAMB18E1
+select -assert-count 4 t:RAM128X1D
+
+# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 
+design -reset
+read_verilog ../common/blockram_params.v
+chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB36E1
+
diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys
deleted file mode 100644
index c1b0ca489..000000000
--- a/tests/arch/xilinx/memory_params.ys
+++ /dev/null
@@ -1,47 +0,0 @@
-## TODO: Not running equivalence checking because BRAM models does not exists
-##       currently. Checking instance counts instead.
-# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
-read_verilog ../common/memory_params.v
-chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB18E1
-
-design -reset
-read_verilog ../common/memory_params.v
-chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB18E1
-
-design -reset
-read_verilog ../common/memory_params.v
-chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB18E1
-
-design -reset
-read_verilog ../common/memory_params.v
-chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB18E1
-
-# Anything memory bits < 1024 -> LUTRAM
-design -reset
-read_verilog ../common/memory_params.v
-chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 0 t:RAMB18E1
-select -assert-count 4 t:RAM128X1D
-
-# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 
-design -reset
-read_verilog ../common/memory_params.v
-chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
-synth_xilinx -top sync_ram_sdp
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB36E1
-